Re: [Qemu-devel] Disable interrupts on Cortex M3 (lm3s6965evb)

[Peter Maydell]

On 5 June 2011 17:32, Sebastian Huber
<address@hidden> wrote:
> On 05/06/11 16:57, Peter Maydell wrote:
>> I agree that the current behaviour is not right. However, to fix
>> this problem you need to work on a larger scale than attempting
>> to apply two line patches which fix your particular use case.
>
> I agree, but you have to start somewhere.  What is "this problem"?  Is
> that we have no execution priority (in the sense of the ARMv7
> architecture, B1.3.2 Exceptions), but instead use a mapping to CPSR_I
> and CPSR_F?

There is some notion of priority, see gic_update()
in hw/arm_gic.c; but it is only within the gic and is not
dealing with v7M specific issues.

At the moment I am mostly just warning you that you're entering
difficult territory; if I have time to read the qemu v7m code
more carefully next week I may have more concrete opinions.

-- PMM