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[Qemu-devel] [PATCH 1/2] SPARC64: fix fnor* and fnand*
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From: |
Tsuneo Saito |
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Subject: |
[Qemu-devel] [PATCH 1/2] SPARC64: fix fnor* and fnand* |
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Date: |
Sat, 23 Jul 2011 11:20:06 +0900 |
Fix the problem that result values are not assigned to the destination
registers.
Signed-off-by: Tsuneo Saito <address@hidden>
---
target-sparc/translate.c | 14 ++++++++------
1 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 15967c5..f68b3bc 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -3980,14 +3980,15 @@ static void disas_sparc_insn(DisasContext * dc)
break;
case 0x062: /* VIS I fnor */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
+ tcg_gen_nor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
cpu_fpr[DFPREG(rs2)]);
- tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
+ tcg_gen_nor_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x063: /* VIS I fnors */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_nor_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ tcg_gen_nor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x064: /* VIS I fandnot2 */
CHECK_FPU_FEATURE(dc, VIS1);
@@ -4047,14 +4048,15 @@ static void disas_sparc_insn(DisasContext * dc)
break;
case 0x06e: /* VIS I fnand */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)],
+ tcg_gen_nand_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)],
cpu_fpr[DFPREG(rs2)]);
- tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1],
+ tcg_gen_nand_i32(cpu_fpr[DFPREG(rd) + 1],
+ cpu_fpr[DFPREG(rs1) + 1],
cpu_fpr[DFPREG(rs2) + 1]);
break;
case 0x06f: /* VIS I fnands */
CHECK_FPU_FEATURE(dc, VIS1);
- tcg_gen_nand_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
+ tcg_gen_nand_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
break;
case 0x070: /* VIS I fand */
CHECK_FPU_FEATURE(dc, VIS1);
--
1.7.5.4