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[Qemu-devel] [PATCH 050/111] m68k: lsl/lsr, clear C flag if shift count
From: |
Bryce Lanham |
Subject: |
[Qemu-devel] [PATCH 050/111] m68k: lsl/lsr, clear C flag if shift count is 0 |
Date: |
Wed, 17 Aug 2011 15:46:55 -0500 |
From: Laurent Vivier <address@hidden>
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/helper.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 5800a4f..21dfcc7 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -739,7 +739,7 @@ uint32_t HELPER(glue(glue(shl, bits),_cc))(CPUState *env,
uint32_t val, uint32_t
shift &= 63; \
if (shift == 0) { \
result = (type)val; \
- cf = env->cc_src & CCF_C; \
+ cf = 0; \
} else if (shift < bits) { \
result = (type)val << shift; \
cf = ((type)val >> (bits - shift)) & 1; \
@@ -768,7 +768,7 @@ uint32_t HELPER(glue(glue(shr, bits), _cc))(CPUState *env,
uint32_t val, uint32_
shift &= 63; \
if (shift == 0) { \
result = (type)val; \
- cf = env->cc_src & CCF_C; \
+ cf = 0; \
} else if (shift < bits) { \
result = (type)val >> shift; \
cf = ((type)val >> (shift - 1)) & 1; \
--
1.7.2.3
- [Qemu-devel] [PATCH 019/111] m68k: add fpu, (continued)
- [Qemu-devel] [PATCH 019/111] m68k: add fpu, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 020/111] m68k: add "byte", "word" and memory shift, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 022/111] m68k: add bitfield_mem, bitfield_reg, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 029/111] m68k: allow fpu to manage double data type with fmove to <ea>, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 030/111] m68k: add FScc instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 031/111] m68k: add single data type to gen_ea, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 039/111] m68k: add abcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 035/111] m68k: improve CC_OP_LOGIC, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 037/111] Correct invalid use of "const void *" with "const uint8_t *", Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 041/111] mm68k: add nbcd instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 050/111] m68k: lsl/lsr, clear C flag if shift count is 0,
Bryce Lanham <=
- [Qemu-devel] [PATCH 043/111] m68k: on 0 bit shift, don't update X flag, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 075/111] m68k: better fpu traces, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 062/111] m68k: FPU rework (draft), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 076/111] m68k: register source operand is always in extended size, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 074/111] m68k: add ftwotox instruction, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 060/111] m68k: remove dead code, Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 045/111] m68k: improve subx, negx instructions Add (byte, word) opsize Add memory access (subx), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 070/111] m68k: initialize FRegs, define pickNaN(), Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 042/111] m68k: set X flag according size of operand Set X flag correctly for addsub, arith_im, addsubq., Bryce Lanham, 2011/08/17
- [Qemu-devel] [PATCH 085/111] m68k: add fatan instruction, Bryce Lanham, 2011/08/17