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[Qemu-devel] [PATCH 5/6] hw/pl061.c: Support GPIOAMSEL register
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 5/6] hw/pl061.c: Support GPIOAMSEL register |
Date: |
Thu, 18 Aug 2011 00:49:37 +0100 |
Support the GPIOAMSEL register found on some Stellaris boards.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/pl061.c | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/hw/pl061.c b/hw/pl061.c
index 27de824..d13746c 100644
--- a/hw/pl061.c
+++ b/hw/pl061.c
@@ -50,6 +50,7 @@ typedef struct {
uint32_t den;
uint32_t cr;
uint32_t float_high;
+ uint32_t amsel;
qemu_irq irq;
qemu_irq out[8];
const unsigned char *id;
@@ -57,7 +58,7 @@ typedef struct {
static const VMStateDescription vmstate_pl061 = {
.name = "pl061",
- .version_id = 1,
+ .version_id = 2,
.minimum_version_id = 1,
.fields = (VMStateField[]) {
VMSTATE_UINT32(locked, pl061_state),
@@ -80,6 +81,7 @@ static const VMStateDescription vmstate_pl061 = {
VMSTATE_UINT32(den, pl061_state),
VMSTATE_UINT32(cr, pl061_state),
VMSTATE_UINT32(float_high, pl061_state),
+ VMSTATE_UINT32_V(amsel, pl061_state, 2),
VMSTATE_END_OF_LIST()
}
};
@@ -157,6 +159,8 @@ static uint32_t pl061_read(void *opaque, target_phys_addr_t
offset)
return s->locked;
case 0x524: /* Commit */
return s->cr;
+ case 0x528: /* Analog mode select */
+ return s->amsel;
default:
hw_error("pl061_read: Bad offset %x\n", (int)offset);
return 0;
@@ -229,6 +233,9 @@ static void pl061_write(void *opaque, target_phys_addr_t
offset,
if (!s->locked)
s->cr = value & 0xff;
break;
+ case 0x528:
+ s->amsel = value & 0xff;
+ break;
default:
hw_error("pl061_write: Bad offset %x\n", (int)offset);
}
--
1.7.1
- [Qemu-devel] [PULL 0/6] misc ARM device fixes, Peter Maydell, 2011/08/17
- [Qemu-devel] [PATCH 6/6] hw/stellaris: Add support for RCC2 register, Peter Maydell, 2011/08/17
- [Qemu-devel] [PATCH 3/6] vexpress, realview: Use pl111, not pl110, Peter Maydell, 2011/08/17
- [Qemu-devel] [PATCH 4/6] hw/pl061: Convert to VMState, Peter Maydell, 2011/08/17
- [Qemu-devel] [PATCH 5/6] hw/pl061.c: Support GPIOAMSEL register,
Peter Maydell <=
- [Qemu-devel] [PATCH 2/6] versatilepb: Implement SYS_CLCD mux control register bits, Peter Maydell, 2011/08/17
- [Qemu-devel] [PATCH 1/6] hw/pl110: Model the PL111 CLCD controller, Peter Maydell, 2011/08/17
- Re: [Qemu-devel] [PULL 0/6] misc ARM device fixes, Anthony Liguori, 2011/08/21