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Re: [Qemu-devel] [PATCH] tcg/ppc64: Fix zero extension code generation b

From: malc
Subject: Re: [Qemu-devel] [PATCH] tcg/ppc64: Fix zero extension code generation bug for ppc64 host
Date: Fri, 9 Sep 2011 19:09:04 +0400 (MSD)
User-agent: Alpine 2.00 (LNX 1167 2008-08-23)

On Fri, 9 Sep 2011, David Gibson wrote:

> From: Thomas Huth <address@hidden>
> The ppc64 code generation backend uses an rldicr (Rotate Left Double
> Immediate and Clear Right) instruction to implement zero extension of
> a 32 bit quantity to a 64 bit quantity (INDEX_op_ext32u_i64).  However
> this is wrong - this instruction clears specified low bits of the
> value, instead of high bits as we require for a zero extension.  It
> should instead use an rldicl (Rotate Left Double Immediate and Clear
> Left) instruction.
> Presumably amongst other things, this causes the SLOF firmware image
> used with -M pseries to not boot on a ppc64 host.
> It appears this bug was exposed by commit
> 0bf1dbdcc935dfc220a93cd990e947e90706aec6 (tcg/ppc64: fix 16/32 mixup)
> which enabled the use of the op_ext32u_i64 operation on the ppc64
> backend.

Bloody ibm blefuscudians... Thanks, applied.



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