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[Qemu-devel] [PATCH v2 0/5] target-arm: Implement UDIV/SDIV and fused mu
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 0/5] target-arm: Implement UDIV/SDIV and fused multiply-accumulate |
Date: |
Mon, 10 Oct 2011 17:24:03 +0100 |
This patch series implements support in QEMU for some (user-mode)
instructions which are present on some recent processors
(eg Cortex-A15).
The new instructions are UDIV/SDIV (previously only available as a Thumb
encoding for R and M-class cores, now an optional extension to ARMv7A),
and the fused-multiply-accumulate instructions VFMA, VFMS, VFNMA, VFNMS.
We don't (yet) support a specific processor for system mode with these
extensions, so they are enabled only for ARM_CPUID_ANY.
The most interesting part of this is the fused multiply-accumulate
support which I have added to softfloat. Although this is only used
by ARM at the moment I've put in some flags which should be sufficient
for the variants provided by other architectures. (Specifically,
x86, Itanium and SPARC64 VI all need the "negate product" flag
since they have "-(a*b)+c" instructions. PPC needs the "negate
result" and "negate addend" flags.)
Changes v1 -> v2:
* incorporated RTH's suggestions in the main "implement fused multiply-add"
patch (except the one about #ifdef placement, which I disagree with)
* added a patch renaming ARM_FEATURE_DIV to ARM_FEATURE_THUMB_DIV; this
splits "core implements Thumb encodings of UDIV,SDIV" from "core implements
ARM encodings of UDIV,SDIV"; we don't have any cores at the moment where
this would make a difference, but they are architecturally distinct and
the split will avoid having to rejig things for R4 support (R4 has only
the Thumb encodings)
* rebased (and dropped the 'reinstate target-specific NaN handling' patch
as it has been committed)
Peter Maydell (5):
target-arm: v6 media multiply space: UNDEF on unassigned encodings
target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV
target-arm: Add ARM UDIV/SDIV support
softfloat: Implement fused multiply-add
target-arm: Implement VFPv4 fused multiply-accumulate insns
fpu/softfloat-specialize.h | 178 ++++++++++++++++++
fpu/softfloat.c | 427 ++++++++++++++++++++++++++++++++++++++++++++
fpu/softfloat.h | 14 ++
target-arm/cpu.h | 4 +-
target-arm/helper.c | 21 ++-
target-arm/helper.h | 3 +
target-arm/translate.c | 118 ++++++++++++-
7 files changed, 757 insertions(+), 8 deletions(-)
- [Qemu-devel] [PATCH v2 0/5] target-arm: Implement UDIV/SDIV and fused multiply-accumulate,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 1/5] target-arm: v6 media multiply space: UNDEF on unassigned encodings, Peter Maydell, 2011/10/10
- [Qemu-devel] [PATCH v2 5/5] target-arm: Implement VFPv4 fused multiply-accumulate insns, Peter Maydell, 2011/10/10
- [Qemu-devel] [PATCH v2 3/5] target-arm: Add ARM UDIV/SDIV support, Peter Maydell, 2011/10/10
- [Qemu-devel] [PATCH v2 2/5] target-arm: Rename ARM_FEATURE_DIV to _THUMB_DIV, Peter Maydell, 2011/10/10
- [Qemu-devel] [PATCH v2 4/5] softfloat: Implement fused multiply-add, Peter Maydell, 2011/10/10