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[Qemu-devel] [PATCH 2/3] target-mips:enabling of 64 bit user mode and fl
From: |
khansa |
Subject: |
[Qemu-devel] [PATCH 2/3] target-mips:enabling of 64 bit user mode and floating point operations MIPS_HFLAG_UX is included in env->hflags so that the address computation for LD instruction does not treated as 32 bit code see gen_op_addr_add() in translate.c |
Date: |
Thu, 8 Dec 2011 10:25:11 +0500 |
From: Khansa Butt <address@hidden>
Signed-off-by: Abdul Qadeer <address@hidden>
---
target-mips/translate.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d5b1c76..452a63b 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12779,6 +12779,10 @@ void cpu_reset (CPUMIPSState *env)
env->hflags |= MIPS_HFLAG_FPU;
}
#ifdef TARGET_MIPS64
+ env->hflags |= MIPS_HFLAG_UX;
+ /* if cpu has FPU, MIPS_HFLAG_F64 must be included in env->hflags
+ so that floating point operations can be emulated */
+ env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
env->hflags |= MIPS_HFLAG_F64;
}
--
1.7.3.4