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From: | Evgeny Voevodin |
Subject: | Re: [Qemu-devel] [PATCH v4 04/11] ARM: exynos4210: IRQ subsystem support. |
Date: | Wed, 21 Dec 2011 19:08:49 +0400 |
User-agent: | Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.9.2.23) Gecko/20110922 Thunderbird/3.1.15 |
On 12/21/2011 05:50 PM, Peter Maydell wrote:
These functions are not actually for splitting CPU and Distributer interfaces. In our board we have two GICs - internal and external. Internal GIC is completelyOn 19 December 2011 11:53, Evgeny Voevodin<address@hidden> wrote:+static uint64_t exynos4210_gic_cpu_read(void *opaque, target_phys_addr_t offset, + unsigned size) +{ + Exynos4210GicState *s = (Exynos4210GicState *) opaque; + DPRINTF_EXYNOS4210_GIC("CPU%d: read offset 0x%x\n", + gic_get_current_cpu(), offset); + return gic_cpu_read(&s->gic, gic_get_current_cpu(), offset& ~0x8000); +}arm_gic.c exposes the CPU and distributor interfaces as their own memory regions now -- you shouldn't need any of this intermediate layer of functions. (Reviewing the rest of this series is on my todo list but I can't guarantee I'll get to it until after Christmas now.) -- PMM
matching arm_gic.c.Internal GIC CPU[n] and Distributer[n] interfaces are at 0x100 and 0x1000 offsets from
0x10500000 base. But external GIC is different. It's CPU[0] interface is at 0x0 offset from 0x10480000 base and CPU[1] interface is at 0x8000 offset from 0x10480000 base It's Distributer[0] interface is at 0x0 offset from 0x10490000 base and Distributer[1] interface is at 0x8000 offset from 0x10490000 base [n] - is corresponding to SMP CPU Core. So, we need these wrapper functions for External GIC.In public accessed documentation internal GIC is not covered for some reason.
-- Kind regards, Evgeny Voevodin, Leading Software Engineer, ASWG, Moscow R&D center, Samsung Electronics e-mail: address@hidden
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