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Re: [Qemu-devel] [PATCH 9/9] arm: increase a9mp interrupts to 160
From: |
Rob Herring |
Subject: |
Re: [Qemu-devel] [PATCH 9/9] arm: increase a9mp interrupts to 160 |
Date: |
Fri, 23 Dec 2011 18:54:34 -0600 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:8.0) Gecko/20111124 Thunderbird/8.0 |
Mark,
On 12/22/2011 12:20 PM, Mark Langsdorf wrote:
> From: Rob Herring <address@hidden>
>
> Signed-off-by: Rob Herring <address@hidden>
> Signed-off-by: Mark Langsdorf <address@hidden>
> ---
> hw/a9mpcore.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
> index 875ae98..93b0498 100644
> --- a/hw/a9mpcore.c
> +++ b/hw/a9mpcore.c
> @@ -13,7 +13,7 @@
> /* Configuration for arm_gic.c:
> * number of external IRQ lines, max number of CPUs, how to ID current CPU
> */
> -#define GIC_NIRQ 96
> +#define GIC_NIRQ 160
> #define NCPU 4
This needs to be run-time. The value gets put in a register and read by
the OS. It breaks platforms expecting 96 irqs.
Rob
- [Qemu-devel] [PATCH v2 0/9] various ARM fixes, Mark Langsdorf, 2011/12/22
- [Qemu-devel] [PATCH v2 4/9] arm: add dummy gic security registers, Mark Langsdorf, 2011/12/22
- [Qemu-devel] [PATCH v2 2/9] arm: Set frequencies for arm_timer, Mark Langsdorf, 2011/12/22
- [Qemu-devel] [PATCH 5/9] ahci: convert ahci_reset to use AHCIState, Mark Langsdorf, 2011/12/22
- [Qemu-devel] [PATCH v2 1/9] arm: add missing scu registers, Mark Langsdorf, 2011/12/22
- [Qemu-devel] [PATCH 9/9] arm: increase a9mp interrupts to 160, Mark Langsdorf, 2011/12/22
- Re: [Qemu-devel] [PATCH 9/9] arm: increase a9mp interrupts to 160,
Rob Herring <=
- [Qemu-devel] [PATCH v2 3/9] arm: add dummy v7 cp15 config_base_register, Mark Langsdorf, 2011/12/22
- [Qemu-devel] [PATCH v2 8/9] Add xgmac ethernet model, Mark Langsdorf, 2011/12/22
- [Qemu-devel] [PATCH 6/9] ahci: add support for non-PCI based controllers, Mark Langsdorf, 2011/12/22
- [Qemu-devel] [PATCH v2 7/9] add L2x0/PL310 cache controller device, Mark Langsdorf, 2011/12/22