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Re: [Qemu-devel] [PATCH v4 5/7] add L2x0/PL310 cache controller device
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v4 5/7] add L2x0/PL310 cache controller device |
Date: |
Wed, 28 Dec 2011 01:32:32 +0000 |
On 28 December 2011 01:24, Mark Langsdorf <address@hidden> wrote:
> + case 0x104:
> + /* aux_ctrl values affect cache_type values */
> + s->aux_ctrl = value;
> + cache_data = (value & (7 << 17)) >> 15;
> + cache_data |= (value & (1 << 16)) >> 16;
> + s->cache_type |= (cache_data << 18) | (cache_data << 6);
> + break;
If you do this this way round, then cache_type is no longer
constant, and you need to reset it in reset and save/load
it in the vmstate. It's probably simpler to fill in the
bits from aux_ctrl when cache_type is read rather than
when aux_ctrl is written. (It seems pretty safe to assume
neither happens very frequently.)
-- PMM
- [Qemu-devel] [PATCH v4 0/7] various ARM fixes, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 4/7] arm: add dummy gic security registers, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 1/7] arm: add missing scu registers, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 3/7] arm: add dummy v7 cp15 config_base_register, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 5/7] add L2x0/PL310 cache controller device, Mark Langsdorf, 2011/12/27
- Re: [Qemu-devel] [PATCH v4 5/7] add L2x0/PL310 cache controller device,
Peter Maydell <=
- [Qemu-devel] [PATCH v4 6/7] Add xgmac ethernet model, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 2/7] arm: Set frequencies for arm_timer, Mark Langsdorf, 2011/12/27
- [Qemu-devel] [PATCH v4 7/7] arm: make the number of GIC interrupts configurable, Mark Langsdorf, 2011/12/27