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[Qemu-devel] [PATCH 01/12] target-xtensa: define TLB_TEMPLATE for MMU-le
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 01/12] target-xtensa: define TLB_TEMPLATE for MMU-less cores |
Date: |
Sat, 18 Feb 2012 21:11:32 +0400 |
TLB_TEMPLATE macro specifies TLB geometry in the core configuration.
Make TLB_TEMPLATE available for region protection core variants,
defining 1 way ITLB and DTLB with 8 entries each.
Signed-off-by: Max Filippov <address@hidden>
---
target-xtensa/overlay_tool.h | 18 ++++++++++++++++--
1 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/target-xtensa/overlay_tool.h b/target-xtensa/overlay_tool.h
index df19cc9..e7c4c3a 100644
--- a/target-xtensa/overlay_tool.h
+++ b/target-xtensa/overlay_tool.h
@@ -251,6 +251,8 @@
.nextint = XCHAL_NUM_EXTINTERRUPTS, \
.extint = EXTINTS
+#if XCHAL_HAVE_PTP_MMU
+
#define TLB_TEMPLATE(ways, refill_way_size, way56) { \
.nways = ways, \
.way_size = { \
@@ -268,11 +270,23 @@
#define DTLB(varway56) \
TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
-#if XCHAL_HAVE_PTP_MMU
#define TLB_SECTION \
.itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
.dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
-#else
+
+#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
+
+#define TLB_TEMPLATE { \
+ .nways = 1, \
+ .way_size = { \
+ 8, \
+ } \
+ }
+
+#define TLB_SECTION \
+ .itlb = TLB_TEMPLATE, \
+ .dtlb = TLB_TEMPLATE
+
#endif
#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
--
1.7.7.6
- [Qemu-devel] [PULL 00/12] target-xtensa queue, Max Filippov, 2012/02/18
- Re: [Qemu-devel] [PULL 00/12] target-xtensa queue, Andreas Färber, 2012/02/18
- [Qemu-devel] [PATCH 01/12] target-xtensa: define TLB_TEMPLATE for MMU-less cores,
Max Filippov <=
- [Qemu-devel] [PATCH 03/12] target-xtensa: fetch 3rd opcode byte only when needed, Max Filippov, 2012/02/18
- [Qemu-devel] [PATCH 02/12] target-xtensa: implement info tlb monitor command, Max Filippov, 2012/02/18
- [Qemu-devel] [PATCH 04/12] target-xtensa: add DEBUGCAUSE SR and configuration, Max Filippov, 2012/02/18
- [Qemu-devel] [PATCH 05/12] target-xtensa: implement instruction breakpoints, Max Filippov, 2012/02/18
- [Qemu-devel] [PATCH 06/12] target-xtensa: add ICOUNT SR and debug exception, Max Filippov, 2012/02/18
- [Qemu-devel] [PATCH 07/12] exec: add missing breaks to the watch_mem_write, Max Filippov, 2012/02/18
- Re: [Qemu-devel] [PATCH 07/12] exec: add missing breaks to the watch_mem_write, Meador Inge, 2012/02/20
- [Qemu-devel] [PATCH 08/12] exec: fix check_watchpoint exiting cpu_loop, Max Filippov, 2012/02/18