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[Qemu-devel] [RFC 09/12] target-lm32: QOM'ify CPU
From: |
Andreas Färber |
Subject: |
[Qemu-devel] [RFC 09/12] target-lm32: QOM'ify CPU |
Date: |
Wed, 14 Mar 2012 18:53:33 +0100 |
Let cpu_lm32_list() enumerate CPU classes sorted alphabetically.
Signed-off-by: Andreas Färber <address@hidden>
---
Makefile.target | 1 +
target-lm32/cpu-qom.h | 77 ++++++++++++++++++++
target-lm32/cpu.c | 188 +++++++++++++++++++++++++++++++++++++++++++++++++
target-lm32/cpu.h | 1 +
target-lm32/helper.c | 142 ++++++++-----------------------------
5 files changed, 297 insertions(+), 112 deletions(-)
create mode 100644 target-lm32/cpu-qom.h
create mode 100644 target-lm32/cpu.c
diff --git a/Makefile.target b/Makefile.target
index 3b7a4da..8c8f4a8 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -90,6 +90,7 @@ libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o
libobj-$(TARGET_ALPHA) += cpu.o
libobj-$(TARGET_ARM) += cpu.o
libobj-$(TARGET_CRIS) += cpu.o
+libobj-$(TARGET_LM32) += cpu.o
libobj-$(TARGET_M68K) += cpu.o
ifeq ($(TARGET_BASE_ARCH), mips)
libobj-y += cpu.o
diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
new file mode 100644
index 0000000..dc3d434
--- /dev/null
+++ b/target-lm32/cpu-qom.h
@@ -0,0 +1,77 @@
+/*
+ * QEMU LatticeMico32 CPU
+ *
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+#ifndef QEMU_LM32_CPU_QOM_H
+#define QEMU_LM32_CPU_QOM_H
+
+#include "qemu/cpu.h"
+#include "cpu.h"
+
+#define TYPE_LM32_CPU "lm32-cpu"
+
+#define LM32_CPU_CLASS(klass) \
+ OBJECT_CLASS_CHECK(LM32CPUClass, (klass), TYPE_LM32_CPU)
+#define LM32_CPU(obj) \
+ OBJECT_CHECK(LM32CPU, (obj), TYPE_LM32_CPU)
+#define LM32_CPU_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(LM32CPUClass, (obj), TYPE_LM32_CPU)
+
+/**
+ * LM32CPUClass:
+ * @parent_reset: The parent class' reset handler.
+ *
+ * A LatticeMico32 CPU model.
+ */
+typedef struct LM32CPUClass {
+ /*< private >*/
+ CPUClass parent_class;
+ /*< public >*/
+
+ void (*parent_reset)(CPUState *cpu);
+
+ uint32_t revision;
+ uint8_t num_interrupts;
+ uint8_t num_breakpoints;
+ uint8_t num_watchpoints;
+ uint32_t features;
+} LM32CPUClass;
+
+/**
+ * LM32CPU:
+ * @env: Legacy CPU state.
+ *
+ * A LatticeMico32 CPU.
+ */
+typedef struct LM32CPU {
+ /*< private >*/
+ CPUState parent_obj;
+ /*< public >*/
+
+ CPULM32State env;
+} LM32CPU;
+
+static inline LM32CPU *cris_env_get_cpu(CPULM32State *env)
+{
+ return LM32_CPU(container_of(env, LM32CPU, env));
+}
+
+#define ENV_GET_CPU(e) CPU(cris_env_get_cpu(e))
+
+
+#endif
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
new file mode 100644
index 0000000..7f5308a
--- /dev/null
+++ b/target-lm32/cpu.c
@@ -0,0 +1,188 @@
+/*
+ * QEMU LatticeMico32 CPU
+ *
+ * Copyright (c) 2010 Michael Walle <address@hidden>
+ * Copyright (c) 2012 SUSE LINUX Products GmbH
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "cpu-qom.h"
+#include "qemu-common.h"
+
+static void lm32_cpu_reset(CPUState *c)
+{
+}
+
+/* CPU models */
+
+typedef struct LM32CPUInfo {
+ const char *name;
+ uint32_t revision;
+ uint8_t num_interrupts;
+ uint8_t num_breakpoints;
+ uint8_t num_watchpoints;
+ uint32_t features;
+} LM32CPUInfo;
+
+static const LM32CPUInfo lm32_cpus[] = {
+ {
+ .name = "lm32-basic",
+ .revision = 3,
+ .num_interrupts = 32,
+ .num_breakpoints = 4,
+ .num_watchpoints = 4,
+ .features = (LM32_FEATURE_SHIFT
+ | LM32_FEATURE_SIGN_EXTEND
+ | LM32_FEATURE_CYCLE_COUNT),
+ },
+ {
+ .name = "lm32-standard",
+ .revision = 3,
+ .num_interrupts = 32,
+ .num_breakpoints = 4,
+ .num_watchpoints = 4,
+ .features = (LM32_FEATURE_MULTIPLY
+ | LM32_FEATURE_DIVIDE
+ | LM32_FEATURE_SHIFT
+ | LM32_FEATURE_SIGN_EXTEND
+ | LM32_FEATURE_I_CACHE
+ | LM32_FEATURE_CYCLE_COUNT),
+ },
+ {
+ .name = "lm32-full",
+ .revision = 3,
+ .num_interrupts = 32,
+ .num_breakpoints = 4,
+ .num_watchpoints = 4,
+ .features = (LM32_FEATURE_MULTIPLY
+ | LM32_FEATURE_DIVIDE
+ | LM32_FEATURE_SHIFT
+ | LM32_FEATURE_SIGN_EXTEND
+ | LM32_FEATURE_I_CACHE
+ | LM32_FEATURE_D_CACHE
+ | LM32_FEATURE_CYCLE_COUNT),
+ }
+};
+
+static uint32_t cfg_by_class(LM32CPUClass *def)
+{
+ uint32_t cfg = 0;
+
+ if (def->features & LM32_FEATURE_MULTIPLY) {
+ cfg |= CFG_M;
+ }
+
+ if (def->features & LM32_FEATURE_DIVIDE) {
+ cfg |= CFG_D;
+ }
+
+ if (def->features & LM32_FEATURE_SHIFT) {
+ cfg |= CFG_S;
+ }
+
+ if (def->features & LM32_FEATURE_SIGN_EXTEND) {
+ cfg |= CFG_X;
+ }
+
+ if (def->features & LM32_FEATURE_I_CACHE) {
+ cfg |= CFG_IC;
+ }
+
+ if (def->features & LM32_FEATURE_D_CACHE) {
+ cfg |= CFG_DC;
+ }
+
+ if (def->features & LM32_FEATURE_CYCLE_COUNT) {
+ cfg |= CFG_CC;
+ }
+
+ cfg |= (def->num_interrupts << CFG_INT_SHIFT);
+ cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
+ cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
+ cfg |= (def->revision << CFG_REV_SHIFT);
+
+ return cfg;
+}
+
+static void lm32_cpu_initfn(Object *obj)
+{
+ LM32CPU *cpu = LM32_CPU(obj);
+ LM32CPUClass *klass = LM32_CPU_GET_CLASS(cpu);
+ CPULM32State *env = &cpu->env;
+
+ memset(env, 0, sizeof(*env));
+ cpu_exec_init(env);
+ env->cpu_model_str = object_get_typename(obj);
+
+ env->features = klass->features;
+ env->num_bps = klass->num_breakpoints;
+ env->num_wps = klass->num_watchpoints;
+ env->cfg = cfg_by_class(klass);
+ env->flags = 0;
+
+ cpu_reset(CPU(cpu));
+}
+
+static void lm32_cpu_class_init(ObjectClass *klass, void *data)
+{
+ CPUClass *cpu_class = CPU_CLASS(klass);
+ LM32CPUClass *k = LM32_CPU_CLASS(klass);
+ const LM32CPUInfo *info = data;
+
+ k->parent_reset = cpu_class->reset;
+ cpu_class->reset = lm32_cpu_reset;
+
+ k->revision = info->revision;
+ k->num_interrupts = info->num_interrupts;
+ k->num_breakpoints = info->num_breakpoints;
+ k->num_watchpoints = info->num_watchpoints;
+ k->features = info->features;
+}
+
+static void cpu_register(const LM32CPUInfo *info)
+{
+ TypeInfo type = {
+ .name = info->name,
+ .parent = TYPE_LM32_CPU,
+ .instance_size = sizeof(LM32CPU),
+ .instance_init = lm32_cpu_initfn,
+ .class_size = sizeof(LM32CPUClass),
+ .class_init = lm32_cpu_class_init,
+ .class_data = (void *)info,
+ };
+
+ type_register_static(&type);
+}
+
+static const TypeInfo lm32_cpu_type_info = {
+ .name = TYPE_LM32_CPU,
+ .parent = TYPE_CPU,
+ .instance_size = sizeof(LM32CPU),
+ .abstract = true,
+ .class_size = sizeof(LM32CPUClass),
+};
+
+static void lm32_cpu_register_types(void)
+{
+ int i;
+
+ type_register_static(&lm32_cpu_type_info);
+ for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
+ cpu_register(&lm32_cpus[i]);
+ }
+}
+
+type_init(lm32_cpu_register_types)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 0902a24..c1be305 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -184,6 +184,7 @@ typedef struct CPULM32State {
} CPULM32State;
+#include "cpu-qom.h"
CPULM32State *cpu_lm32_init(const char *cpu_model);
void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index 5db8f8d..e89cc0e 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -80,139 +80,57 @@ void do_interrupt(CPULM32State *env)
}
}
-typedef struct {
- const char *name;
- uint32_t revision;
- uint8_t num_interrupts;
- uint8_t num_breakpoints;
- uint8_t num_watchpoints;
- uint32_t features;
-} LM32Def;
+typedef struct LM32CPUListState {
+ fprintf_function cpu_fprintf;
+ FILE *file;
+} LM32CPUListState;
-static const LM32Def lm32_defs[] = {
- {
- .name = "lm32-basic",
- .revision = 3,
- .num_interrupts = 32,
- .num_breakpoints = 4,
- .num_watchpoints = 4,
- .features = (LM32_FEATURE_SHIFT
- | LM32_FEATURE_SIGN_EXTEND
- | LM32_FEATURE_CYCLE_COUNT),
- },
- {
- .name = "lm32-standard",
- .revision = 3,
- .num_interrupts = 32,
- .num_breakpoints = 4,
- .num_watchpoints = 4,
- .features = (LM32_FEATURE_MULTIPLY
- | LM32_FEATURE_DIVIDE
- | LM32_FEATURE_SHIFT
- | LM32_FEATURE_SIGN_EXTEND
- | LM32_FEATURE_I_CACHE
- | LM32_FEATURE_CYCLE_COUNT),
- },
- {
- .name = "lm32-full",
- .revision = 3,
- .num_interrupts = 32,
- .num_breakpoints = 4,
- .num_watchpoints = 4,
- .features = (LM32_FEATURE_MULTIPLY
- | LM32_FEATURE_DIVIDE
- | LM32_FEATURE_SHIFT
- | LM32_FEATURE_SIGN_EXTEND
- | LM32_FEATURE_I_CACHE
- | LM32_FEATURE_D_CACHE
- | LM32_FEATURE_CYCLE_COUNT),
- }
-};
-
-void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
+/* Sort alphabetically. */
+static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
{
- int i;
+ ObjectClass *class_a = OBJECT_CLASS(a);
+ ObjectClass *class_b = OBJECT_CLASS(b);
- cpu_fprintf(f, "Available CPUs:\n");
- for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
- cpu_fprintf(f, " %s\n", lm32_defs[i].name);
- }
+ return strcasecmp(object_class_get_name(class_a),
+ object_class_get_name(class_b));
}
-static const LM32Def *cpu_lm32_find_by_name(const char *name)
+static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
- if (strcasecmp(name, lm32_defs[i].name) == 0) {
- return &lm32_defs[i];
- }
- }
+ ObjectClass *klass = data;
+ LM32CPUListState *s = user_data;
- return NULL;
+ (*s->cpu_fprintf)(s->file, " %s\n",
+ object_class_get_name(klass));
}
-static uint32_t cfg_by_def(const LM32Def *def)
+void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
{
- uint32_t cfg = 0;
-
- if (def->features & LM32_FEATURE_MULTIPLY) {
- cfg |= CFG_M;
- }
+ LM32CPUListState s = {
+ .file = f,
+ .cpu_fprintf = cpu_fprintf,
+ };
+ GSList *list;
- if (def->features & LM32_FEATURE_DIVIDE) {
- cfg |= CFG_D;
- }
-
- if (def->features & LM32_FEATURE_SHIFT) {
- cfg |= CFG_S;
- }
-
- if (def->features & LM32_FEATURE_SIGN_EXTEND) {
- cfg |= CFG_X;
- }
-
- if (def->features & LM32_FEATURE_I_CACHE) {
- cfg |= CFG_IC;
- }
-
- if (def->features & LM32_FEATURE_D_CACHE) {
- cfg |= CFG_DC;
- }
-
- if (def->features & LM32_FEATURE_CYCLE_COUNT) {
- cfg |= CFG_CC;
- }
-
- cfg |= (def->num_interrupts << CFG_INT_SHIFT);
- cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
- cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
- cfg |= (def->revision << CFG_REV_SHIFT);
-
- return cfg;
+ list = object_class_get_list(TYPE_LM32_CPU, false);
+ list = g_slist_sort(list, lm32_cpu_list_compare);
+ cpu_fprintf(f, "Available CPUs:\n");
+ g_slist_foreach(list, lm32_cpu_list_entry, &s);
+ g_slist_free(list);
}
CPULM32State *cpu_lm32_init(const char *cpu_model)
{
+ LM32CPU *cpu;
CPULM32State *env;
- const LM32Def *def;
static int tcg_initialized;
- def = cpu_lm32_find_by_name(cpu_model);
- if (!def) {
+ if (object_class_by_name(cpu_model) == NULL) {
return NULL;
}
+ cpu = LM32_CPU(object_new(cpu_model));
+ env = &cpu->env;
- env = g_malloc0(sizeof(CPULM32State));
-
- env->features = def->features;
- env->num_bps = def->num_breakpoints;
- env->num_wps = def->num_watchpoints;
- env->cfg = cfg_by_def(def);
- env->flags = 0;
-
- cpu_exec_init(env);
- cpu_state_reset(env);
qemu_init_vcpu(env);
if (!tcg_initialized) {
--
1.7.7
- Re: [Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC, (continued)
- [Qemu-devel] [RFC 00/12] QOM'ify remaining CPUs, Andreas Färber, 2012/03/15
- [Qemu-devel] [RFC 04/12] target-alpha: QOM'ify CPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [RFC 07/12] target-ppc: Prepare finalizer for PowerPCCPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [RFC 10/12] target-microblaze: QOM'ify CPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [RFC 06/12] target-ppc: QOM'ify CPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [RFC 03/12] target-m68k: QOM'ify CPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [RFC 08/12] target-cris: QOM'ify CPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [RFC 09/12] target-lm32: QOM'ify CPU,
Andreas Färber <=
- [Qemu-devel] [RFC 01/12] target-s390x: QOM'ify CPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [RFC 12/12] target-xtensa: QOM'ify CPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [RFC 11/12] target-sparc: QOM'ify CPU, Andreas Färber, 2012/03/14
[Qemu-devel] [RFC 02/12] target-mips: QOM'ify CPU, Andreas Färber, 2012/03/14