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Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU
From: |
Andreas Färber |
Subject: |
Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU |
Date: |
Fri, 23 Mar 2012 17:53:40 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120215 Thunderbird/10.0.2 |
Am 14.03.2012 08:32, schrieb Guan Xuetao:
> On Wed, 2012-03-14 at 02:39 +0100, Andreas Färber wrote:
>> Based on qom-cpu v4 and object_class_get_list() v2, this series converts
>> the UniCore32 CPU to QOM. Code-wise, target-unicore32 is pretty close to
>> target-arm and faces a similar issue of CPU-dependent init code, so let's
>> tackle it next.
>>
>> Patch 1 adds a UniCore32 CPU guest core (TCG) section to MAINTAINERS,
>> so that the target-unicore32 author gets notified of patches against his
>> code.
>>
>> Patch 2, based on feedback from Guan Xuetao, changes the license of most
>> target-unicore32 files from GPLv2 to GPLv2+. Anthony had contributed a
>> qemu_malloc() -> g_malloc() substitution that he can't relicense at this
>> time,
>> so leave that as GPLv2 and declare my following patches explicitly as GPLv2+.
>>
>> Patch 2 embeds CPUUniCore32State into UniCore32CPU. My new cpu-qom.h header
>> can be GPLv2+, but into cpu.c we're moving helper.c code so make it GPLv2
>> for now.
>>
>> Patches 4-7 move code out of the uc32_cpu_init() function and into classes.
>
> I pulled the latest qemu code, but these patches seems to rely on the
> former qom-cpu v4 series.
That series has been applied in the meantime, so unicore32 should no
longer depend on other series.
> Could you tell me where I can pull the testable branch/tree?
Sorry, repo.or.cz was having problems at the time of posting, this v1
series is now available at:
git://repo.or.cz/qemu/afaerber.git qom-cpu-unicore32.v1
http://repo.or.cz/w/qemu/afaerber.git/shortlog/refs/heads/qom-cpu-unicore32.v1
I've added links to the Wiki for my work-in-progress branches on GitHub:
http://wiki.qemu.org/Features/QOM/CPU
Today I've reworked the preceding ARM series and rebased onto v5; I
still need to revisit the table-driven class initialization before
sending out a v2. MAINTAINERS and licenses are already adjusted.
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
- [Qemu-devel] [PATCH 1/7] MAINTAINERS: Add entry for UniCore32, (continued)
[Qemu-devel] [PATCH 5/7] target-unicore32: Store cp0 c1_sys in UniCore32CPUClass, Andreas Färber, 2012/03/13
[Qemu-devel] [PATCH 7/7] target-unicore32: Store ucf64 fpscr in UniCore32CPUClass, Andreas Färber, 2012/03/13
[Qemu-devel] [PATCH 6/7] target-unicore32: Store feature flags in UniCore32CPUClass, Andreas Färber, 2012/03/13
Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU, Guan Xuetao, 2012/03/14
- Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU,
Andreas Färber <=
Re: [Qemu-devel] [PATCH 0/7] QOM'ify UniCore32 CPU, Blue Swirl, 2012/03/14
[Qemu-devel] [PATCH 00/12] QOM'ify SuperH CPU and SH7750 SoC, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH 02/12] target-sh4: Do not reset features on reset, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH 10/12] target-sh4: Make update_itlb_use() take SuperHCPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH 09/12] target-sh4: Make copy_utlb_entry_itlb() take SuperHCPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH 11/12] target-sh4: Make itlb_replacement() use SuperHCPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH 04/12] target-sh4: Make cpu_sh4_invalidate_tlb() take SuperHCPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH 08/12] target-sh4: Make get_{physical, mmu}_address() take SuperHCPU, Andreas Färber, 2012/03/14
- [Qemu-devel] [PATCH 07/12] target-sh4: Make cpu_sh4_{read, write}_mmaped_{i, u}tlb_addr() take CPU, Andreas Färber, 2012/03/14