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[Qemu-devel] [PATCH 31/32] target-arm: Remove remaining old cp15 infrast
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 31/32] target-arm: Remove remaining old cp15 infrastructure |
Date: |
Sun, 15 Apr 2012 14:46:24 +0100 |
There are now no uses of the old cp15 infrastructure,
so it can be deleted.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 39 -------------------------------
target-arm/helper.h | 3 --
target-arm/translate.c | 59 +-----------------------------------------------
3 files changed, 1 insertions(+), 100 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index aef2e26..3c5671d 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1422,16 +1422,6 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env,
target_ulong address, int rw,
return 1;
}
-void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
-{
- cpu_abort(env, "cp15 insn %08x\n", insn);
-}
-
-uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
-{
- cpu_abort(env, "cp15 insn %08x\n", insn);
-}
-
/* These should probably raise undefined insn exceptions. */
void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
{
@@ -2158,35 +2148,6 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUARMState
*env, target_ulong addr)
return phys_addr;
}
-void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
-{
- int op1;
- int op2;
- int crm;
-
- op1 = (insn >> 21) & 7;
- op2 = (insn >> 5) & 7;
- crm = insn & 0xf;
- /* ??? For debugging only. Should raise illegal instruction exception. */
- cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
- (insn >> 16) & 0xf, crm, op1, op2);
-}
-
-uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
-{
- int op1;
- int op2;
- int crm;
-
- op1 = (insn >> 21) & 7;
- op2 = (insn >> 5) & 7;
- crm = insn & 0xf;
- /* ??? For debugging only. Should raise illegal instruction exception. */
- cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
- (insn >> 16) & 0xf, crm, op1, op2);
- return 0;
-}
-
void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
{
if ((env->uncached_cpsr & CPSR_M) == mode) {
diff --git a/target-arm/helper.h b/target-arm/helper.h
index a0034ae..21e9cfe 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -59,9 +59,6 @@ DEF_HELPER_0(cpsr_read, i32)
DEF_HELPER_3(v7m_msr, void, env, i32, i32)
DEF_HELPER_2(v7m_mrs, i32, env, i32)
-DEF_HELPER_3(set_cp15, void, env, i32, i32)
-DEF_HELPER_2(get_cp15, i32, env, i32)
-
DEF_HELPER_3(set_cp_reg, void, env, ptr, i32)
DEF_HELPER_2(get_cp_reg, i32, env, ptr)
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 09e2165..ea5a1a6 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2439,55 +2439,6 @@ static int disas_dsp_insn(CPUARMState *env, DisasContext
*s, uint32_t insn)
return 1;
}
-/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
- instruction is not defined. */
-static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
-{
- uint32_t rd;
- TCGv tmp, tmp2;
-
- /* M profile cores use memory mapped registers instead of cp15. */
- if (arm_feature(env, ARM_FEATURE_M))
- return 1;
-
- if ((insn & (1 << 25)) == 0) {
- return 1;
- }
- if ((insn & (1 << 4)) == 0) {
- /* cdp */
- return 1;
- }
-
- if (IS_USER(s)) {
- return 1;
- }
-
- rd = (insn >> 12) & 0xf;
-
- tmp2 = tcg_const_i32(insn);
- if (insn & ARM_CP_RW_BIT) {
- tmp = tcg_temp_new_i32();
- gen_helper_get_cp15(tmp, cpu_env, tmp2);
- /* If the destination register is r15 then sets condition codes. */
- if (rd != 15)
- store_reg(s, rd, tmp);
- else
- tcg_temp_free_i32(tmp);
- } else {
- tmp = load_reg(s, rd);
- gen_helper_set_cp15(cpu_env, tmp2, tmp);
- tcg_temp_free_i32(tmp);
- /* Normally we would always end the TB here, but Linux
- * arch/arm/mach-pxa/sleep.S expects two instructions following
- * an MMU enable to execute from cache. Imitate this behaviour. */
- if (!arm_feature(env, ARM_FEATURE_XSCALE) ||
- (insn & 0x0fff0fff) != 0x0e010f10)
- gen_lookup_tb(s);
- }
- tcg_temp_free_i32(tmp2);
- return 0;
-}
-
#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
#define VFP_SREG(insn, bigbit, smallbit) \
((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
@@ -6387,15 +6338,7 @@ static int disas_coproc_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
return 0;
}
- /* Fallback code: handle coprocessor registers not yet converted
- * to ARMCPRegInfo.
- */
- switch (cpnum) {
- case 15:
- return disas_cp15_insn (env, s, insn);
- default:
- return 1;
- }
+ return 1;
}
--
1.7.1
- [Qemu-devel] [PATCH 21/32] target-arm: convert cp15 crn=7 registers, (continued)
- [Qemu-devel] [PATCH 21/32] target-arm: convert cp15 crn=7 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 17/32] target-arm: Convert cp15 crn=10 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 24/32] target-arm: Convert cp15 crn=1 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 20/32] target-arm: Convert cp15 VA-PA translation registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 16/32] target-arm: Convert cp15 crn=13 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 29/32] target-arm: Remove c0_cachetype CPUARMState field, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 05/32] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 11/32] target-arm: Convert performance monitor registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 04/32] hw/pxa2xx_pic: Convert coprocessor registers to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 23/32] target-arm: Convert cp15 crn=9 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 31/32] target-arm: Remove remaining old cp15 infrastructure,
Peter Maydell <=
- [Qemu-devel] [PATCH 08/32] target-arm: Convert TEECR, TEEHBR to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 15/32] target-arm: Convert cp15 crn=2 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 02/32] hw/pxa2xx: Convert cp14 perf registers to new scheme, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 14/32] target-arm: Convert MMU fault status cp15 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 28/32] target-arm: Convert final ID registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 30/32] target-arm: Move block cache ops to new cp15 framework, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 18/32] target-arm: Convert cp15 crn=15 registers, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 03/32] hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 32/32] target-arm: Remove ARM_CPUID_* macros, Peter Maydell, 2012/04/15
- [Qemu-devel] [PATCH 12/32] target-arm: Convert generic timer cp15 regs, Peter Maydell, 2012/04/15