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Re: [Qemu-devel] [PATCH v2 11/14] target-arm: Move cache ID register set
From: |
Andreas Färber |
Subject: |
Re: [Qemu-devel] [PATCH v2 11/14] target-arm: Move cache ID register setup to cpu specific init fns |
Date: |
Fri, 20 Apr 2012 18:00:29 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:11.0) Gecko/20120312 Thunderbird/11.0 |
Am 14.04.2012 18:42, schrieb Peter Maydell:
> Move cache ID register reset out of cpu_reset_model_id() by
> creating a field for the reset value in ARMCPU and setting it
> up in the cpu specific init functions.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target-arm/cpu-qom.h | 5 +++++
> target-arm/cpu.c | 11 +++++++++++
> target-arm/helper.c | 13 ++-----------
> 3 files changed, 18 insertions(+), 11 deletions(-)
[...]
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 924aaed..63de462 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -269,6 +269,10 @@ static void cortex_a8_initfn(Object *obj)
> cpu->id_isar2 = 0x21232031;
> cpu->id_isar3 = 0x11112131;
> cpu->id_isar4 = 0x00111142;
> + cpu->clidr = (1 << 27) | (2 << 24) | 3;
> + cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
> + cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
> + cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
> }
>
> static void cortex_a9_initfn(Object *obj)
> @@ -302,6 +306,9 @@ static void cortex_a9_initfn(Object *obj)
> cpu->id_isar2 = 0x21232041;
> cpu->id_isar3 = 0x11112131;
> cpu->id_isar4 = 0x00111142;
> + cpu->clidr = (1 << 27) | (2 << 24) | 3;
Copy&paste, should be (1 << 27) | (1 << 24) | 3.
/-F
> + cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
> + cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
> }
>
> static void cortex_a15_initfn(Object *obj)
[...]
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index fb618a7..5cbc7e0 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -25,21 +25,10 @@ static void cpu_reset_model_id(CPUARMState *env, uint32_t
> id)
> case ARM_CPUID_ARM11MPCORE:
> break;
> case ARM_CPUID_CORTEXA8:
> - env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
> - env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
> - env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
> - env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
> break;
> case ARM_CPUID_CORTEXA9:
> - env->cp15.c0_clid = (1 << 27) | (1 << 24) | 3;
> - env->cp15.c0_ccsid[0] = 0xe00fe015; /* 16k L1 dcache. */
> - env->cp15.c0_ccsid[1] = 0x200fe015; /* 16k L1 icache. */
> break;
> case ARM_CPUID_CORTEXA15:
> - env->cp15.c0_clid = 0x0a200023;
> - env->cp15.c0_ccsid[0] = 0x701fe00a; /* 32K L1 dcache */
> - env->cp15.c0_ccsid[1] = 0x201fe00a; /* 32K L1 icache */
> - env->cp15.c0_ccsid[2] = 0x711fe07a; /* 4096K L2 unified cache */
> break;
> case ARM_CPUID_CORTEXM3:
> break;
[snip]
--
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[Qemu-devel] [PATCH v2 05/14] target-arm: Move CTR setup to per cpu init fns, Peter Maydell, 2012/04/14
[Qemu-devel] [PATCH v2 08/14] target-arm: Move iWMMXT wCID reset to cpu_state_reset, Peter Maydell, 2012/04/14
[Qemu-devel] [PATCH v2 13/14] target-arm: Move reset handling to arm_cpu_reset, Peter Maydell, 2012/04/14