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[Qemu-devel] [PATCH qom-next v2 20/33] target-arm: Convert cp15 MMU TLB
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH qom-next v2 20/33] target-arm: Convert cp15 MMU TLB control |
Date: |
Mon, 14 May 2012 20:03:19 +0100 |
Convert cp15 MMU TLB control (crn=8) to new scheme.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 63 ++++++++++++++++++++++++++++++++++----------------
1 files changed, 43 insertions(+), 20 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c371224..d57f943 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -93,6 +93,38 @@ static int contextidr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
return 0;
}
+static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Invalidate all (TLBIALL) */
+ tlb_flush(env, 1);
+ return 0;
+}
+
+static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
+ tlb_flush_page(env, value & TARGET_PAGE_MASK);
+ return 0;
+}
+
+static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Invalidate by ASID (TLBIASID) */
+ tlb_flush(env, value == 0);
+ return 0;
+}
+
+static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
+ tlb_flush_page(env, value & TARGET_PAGE_MASK);
+ return 0;
+}
+
static const ARMCPRegInfo cp_reginfo[] = {
/* DBGDIDR: just RAZ. In particular this means the "debug architecture
* version" bits will read as a reserved value, which should cause
@@ -116,6 +148,17 @@ static const ARMCPRegInfo cp_reginfo[] = {
*/
{ .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
.opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
+ /* MMU TLB control. Note that the wildcarding means we cover not just
+ * the unified TLB ops but also the dside/iside/inner-shareable variants.
+ */
+ { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
+ .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
+ { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
+ .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
+ { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
+ .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
+ { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
+ .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
REGINFO_SENTINEL
};
@@ -1840,24 +1883,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn,
uint32_t val)
}
}
break;
- case 8: /* MMU TLB control. */
- switch (op2) {
- case 0: /* Invalidate all (TLBIALL) */
- tlb_flush(env, 1);
- break;
- case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
- tlb_flush_page(env, val & TARGET_PAGE_MASK);
- break;
- case 2: /* Invalidate by ASID (TLBIASID) */
- tlb_flush(env, val == 0);
- break;
- case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
- tlb_flush_page(env, val & TARGET_PAGE_MASK);
- break;
- default:
- goto bad_reg;
- }
- break;
case 9:
if (arm_feature(env, ARM_FEATURE_OMAPCP))
break;
@@ -2070,8 +2095,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
/* FIXME: Should only clear Z flag if destination is r15. */
env->ZF = 0;
return 0;
- case 8: /* MMU TLB control. */
- goto bad_reg;
case 9:
switch (crm) {
case 0: /* Cache lockdown */
--
1.7.1
- [Qemu-devel] [PATCH qom-next v2 33/33] target-arm: Remove ARM_CPUID_* macros, (continued)
- [Qemu-devel] [PATCH qom-next v2 33/33] target-arm: Remove ARM_CPUID_* macros, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 31/33] target-arm: Move block cache ops to new cp15 framework, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 29/33] target-arm: Convert final ID registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 28/33] target-arm: Convert MPIDR, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 25/33] target-arm: Convert cp15 crn=1 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 26/33] target-arm: Convert cp15 crn=0 crm={1, 2} feature registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 27/33] target-arm: Convert cp15 cache ID registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 23/33] target-arm: Convert cp15 crn=6 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 21/33] target-arm: Convert cp15 VA-PA translation registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 24/33] target-arm: Convert cp15 crn=9 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 20/33] target-arm: Convert cp15 MMU TLB control,
Peter Maydell <=
- [Qemu-devel] [PATCH qom-next v2 22/33] target-arm: convert cp15 crn=7 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 08/33] target-arm: Convert debug registers to cp_reginfo, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 12/33] target-arm: Convert performance monitor registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 14/33] target-arm: Convert cp15 c3 register, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 15/33] target-arm: Convert MMU fault status cp15 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 13/33] target-arm: Convert generic timer cp15 regs, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 18/33] target-arm: Convert cp15 crn=10 registers, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 06/33] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 05/33] hw/pxa2xx_pic: Convert coprocessor registers to new scheme, Peter Maydell, 2012/05/14
- [Qemu-devel] [PATCH qom-next v2 01/33] target-arm: Fix 11MPCore cache type register value, Peter Maydell, 2012/05/14