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Re: [Qemu-devel] [PATCH V4 0/5] Ehnahced SSI bus support + M25P80 SPI fl
From: |
Paul Brook |
Subject: |
Re: [Qemu-devel] [PATCH V4 0/5] Ehnahced SSI bus support + M25P80 SPI flash + Xilinx SPI controller |
Date: |
Tue, 5 Jun 2012 02:34:08 +0100 |
User-agent: |
KMail/1.13.7 (Linux/3.2.0-2-amd64; KDE/4.7.4; x86_64; ; ) |
> Patch 1 Enhances SSI bus support to properly support multiple attached
> devices. An api is provided for SSI/SPI masters to select a particular
> device attached to the bus.
>
> Patch 2 is a device model for the m25p80 style SPI flash chip.
>
> Patch 3 is the Xilinx XPS SPI contoller. Its a sysbus device that
> instantiates a ssi bus, and interfaces the two (as per the controllers
> functionality)
>
> Patch 4 instantiates the XPS SPI controller in the petalogix ML605
> reference platform and connects two m25p80s to it.
>
> Patch 5 updates the stellaris machine model to use the multi slave SSI
> support
I'm still not convinced modelling this as a multipoint bus is a good idea. If
nothing else you've failed to model the case where multiple slaves are
selected simultanously. Given the chip selects are actual wires, not part of
the bus itself, I think multiple point-point busses are a better fit.
For the stellaris device we still have the synthetic mux device and
intermediate bus.
Paul
- [Qemu-devel] [PATCH V4 0/5] Ehnahced SSI bus support + M25P80 SPI flash + Xilinx SPI controller, Peter A. G. Crosthwaite, 2012/06/04
- [Qemu-devel] [PATCH V4 1/5] SSI: Built in multiple device support, Peter A. G. Crosthwaite, 2012/06/04
- [Qemu-devel] [PATCH V4 2/5] m25p80: initial verion, Peter A. G. Crosthwaite, 2012/06/04
- [Qemu-devel] [PATCH V4 4/5] petalogix-ml605: added spi controller with m25p80, Peter A. G. Crosthwaite, 2012/06/04
- [Qemu-devel] [PATCH V4 3/5] xilinx_spi: initial version, Peter A. G. Crosthwaite, 2012/06/04
- [Qemu-devel] [PATCH V4 5/5] stellaris: Updated spi bus implementation, Peter A. G. Crosthwaite, 2012/06/04
- Re: [Qemu-devel] [PATCH V4 0/5] Ehnahced SSI bus support + M25P80 SPI flash + Xilinx SPI controller,
Paul Brook <=