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Re: [Qemu-devel] [RFC] Proposal: PCI/PCIe: inbound BAR0 emulation for PC
Re: [Qemu-devel] [RFC] Proposal: PCI/PCIe: inbound BAR0 emulation for PCI controller (Root Complex)
Fri, 8 Jun 2012 14:08:30 -0500
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On 06/08/2012 06:01 AM, Benjamin Herrenschmidt wrote:
> From there, AFAIK, the MSI code will simply do stl_le_phys, which I
> -believe- will hit a BAR that does MMIO decoding for those addresses,
> but I'll let people knowing qemu more in depth reply whether that's true
> or not.
We may run into trouble once we have an in-kernel MPIC (as we do in our
internal tree), as QEMU won't be the right destination for the MSI.
This is also a problem for the QEMU command line inspecting such MMIO
addresses. I guess the answer is to make QEMU properly aware of
kernel-emulated MMIO regions.
>> 1. Whenever PCI device does need DMA then these windows (inbound and
>> outbound ATMUs registers) need to used to translate pci address to
>> system physical address (Sometime we also call this as cpu address
>> space). This will probably be done by : [Qemu-devel] [PATCH 00/12]
>> IOMMU Infrastructure : patch-set ( I am trying to understand these
>> patches :-))
> Yes, that's basically it. The patches allow you to add a set of routines
> that will be used for translating DMA accesses to system memory along
> with map/unmap operations etc...
How easy is it to have multi-level translation -- PCI controller
translates PCI transactions to host DMA addresses, and the system IOMMU
translates that into a physical address?