Re: [Qemu-devel] [RFC] QOMification of AXI streams

[Benjamin Herrenschmidt]

On Thu, 2012-06-14 at 04:31 +0200, Edgar E. Iglesias wrote:
> > An AXI device might issue a cycle on the AXI portion, that can be
> > decoded by either a sibling AXI device ... or go up. In most cases
> 
> No, it doesn't really go up.. This is where we disagree.

Well, not really indeed as the memory subsystem is just another sibling
in this specific case, bad choice of words here. Though it does go "up"
in a way if you are in a cache coherent system thanks to snooping :-)
But right, memory is just a sibling.

> > though, "upstream" is some kind of substractive decoding (ie. anything
> > -not- decoded by a sibling goes up).
> 
> I've never seen this happen, but I won't say it doesn't exist because
> you'll find all kinds of HW out there that'll do all kind of stuff
> you wouldn't imagine.

Its quite common. You seem to have a vision limited to a single flat bus
with all the devices connected to it :-) The minute you start having bus
hierarchies things become much more interesting... Even on ARM, with PCI
for example.

> > This gets even more obvious with PCI of course. Then add a b43 wifi card
> > on PCI, you have AXI -> PCI -> SSB (silicon backplane). Now what happens
> > when one of the sub-devices on SBB (the MAC interface for example) does
> > a bus master ? You have at least 2 layers to cross before you hit your
> > processor bus. 
> > 
> > Add iommu's to the soup and you get into a serious mess :-)
> 
> IOmmus messify things a bit, but the translation is only done from
> the masters above the iommu going down theough the iommu. Not
> vice versa. At least AFAIK.

Sure, for the very simple reason that the iommu typically sits behind
the master. So the other direction is handled by the CPU's MMU.

However, iommu's aren't necessarily at the top level either ... some
designs have a global one that handle all type of devices, some designs
have them in the PCI bridge itself, etc...

Cheers,
Ben.