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Re: [Qemu-devel] [PATCH 1/2] ppc64: Rudimentary Support for extra page s

From: Alexander Graf
Subject: Re: [Qemu-devel] [PATCH 1/2] ppc64: Rudimentary Support for extra page sizes on server CPUs
Date: Tue, 19 Jun 2012 22:57:31 +0200

On 19.06.2012, at 07:56, Benjamin Herrenschmidt wrote:

> More recent Power server chips (i.e. based on the 64 bit hash MMU)
> support more than just the traditional 4k and 16M page sizes.  This
> can get quite complicated, because which page sizes are supported,
> which combinations are supported within an MMU segment and how these
> page sizes are encoded both in the SLB entry and the hash PTE can vary
> depending on the CPU model (they are not specified by the
> architecture).  In addition the firmware or hypervisor may not permit
> use of certain page sizes, for various reasons.  Whether various page
> sizes are supported on KVM, for example, depends on whether the PR or
> HV variant of KVM is in use, and on the page size of the memory
> backing the guest's RAM.
> This patch adds information to the CPUState and cpu defs to describe
> the supported page sizes and encodings.  Since TCG does not yet
> support any extended page sizes, we just set this to NULL in the
> static CPU definitions, expanding this to the default 4k and 16M page
> sizes when we initialize the cpu state.  When using KVM, however, we
> instead determine available page sizes using the new
> KVM_PPC_GET_SMMU_INFO call.  For old kernels without that call, we use
> some defaults, with some guesswork which should do the right thing for
> existing HV and PR implementations.  The fallback might not be correct
> for future versions, but that's ok, because they'll have
> Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> Signed-off-by: David Gibson <address@hidden>

Thanks, applied both to ppc-next.


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