[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 01/33] target-arm: Fix 11MPCore cache type register
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 01/33] target-arm: Fix 11MPCore cache type register value |
Date: |
Wed, 20 Jun 2012 13:26:49 +0100 |
Make the 11MPCore report a valid value in its cache type register
(the previous value appears to have been incorrectly copied from
the 1136/1176). In particular, do not report that we have an
aliasing VIPT cache, because this causes Linux to attempt to use
the v6 block cache ops which the 11MPCore doesn't actually have.
(This causes no problems currently because we over-broadly provide
those ops on all cores, but prevents us correctly narrowing the
block ops down to those cores which actually implement them.)
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7eb323a..934894b 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -307,7 +307,7 @@ static void arm11mpcore_initfn(Object *obj)
cpu->reset_fpsid = 0x410120b4;
cpu->mvfr0 = 0x11111111;
cpu->mvfr1 = 0x00000000;
- cpu->ctr = 0x1dd20d2;
+ cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
cpu->id_pfr0 = 0x111;
cpu->id_pfr1 = 0x1;
cpu->id_dfr0 = 0;
--
1.7.1
- [Qemu-devel] [PATCH 19/33] target-arm: Convert cp15 crn=15 registers, (continued)
- [Qemu-devel] [PATCH 19/33] target-arm: Convert cp15 crn=15 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 04/33] hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 20/33] target-arm: Convert cp15 MMU TLB control, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 25/33] target-arm: Convert cp15 crn=1 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 06/33] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 29/33] target-arm: Convert final ID registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 15/33] target-arm: Convert MMU fault status cp15 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 12/33] target-arm: Convert performance monitor registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 11/33] target-arm: Convert TLS registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 07/33] target-arm: Add register_cp_regs_for_features(), Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 01/33] target-arm: Fix 11MPCore cache type register value,
Peter Maydell <=
- [Qemu-devel] [PATCH 18/33] target-arm: Convert cp15 crn=10 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 21/33] target-arm: Convert cp15 VA-PA translation registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 24/33] target-arm: Convert cp15 crn=9 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 23/33] target-arm: Convert cp15 crn=6 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 27/33] target-arm: Convert cp15 cache ID registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 05/33] hw/pxa2xx_pic: Convert coprocessor registers to new scheme, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 17/33] target-arm: Convert cp15 crn=13 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 33/33] target-arm: Remove ARM_CPUID_* macros, Peter Maydell, 2012/06/20
- Re: [Qemu-devel] [PULL 00/33] target-arm queue, Blue Swirl, 2012/06/24