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[Qemu-devel] [PATCH 18/33] target-arm: Convert cp15 crn=10 registers
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 18/33] target-arm: Convert cp15 crn=10 registers |
Date: |
Wed, 20 Jun 2012 13:27:06 +0100 |
We RAZ/WI the entire block of crn=10 registers. Note that this
actually covers not just the implementation-defined TLB
lockdown registers but also a number of v7 VMSA memory
attribute registers which we would need to implement to
support TEX remap. We retain the previous QEMU behaviour
in this conversion, though.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 11 +++++------
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3cffa00..5fa4ed5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -106,6 +106,11 @@ static const ARMCPRegInfo cp_reginfo[] = {
{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 =
1,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
.resetvalue = 0, .writefn = contextidr_write },
+ /* ??? This covers not just the impdef TLB lockdown registers but also
+ * some v7VMSA registers relating to TEX remap, so it is overly broad.
+ */
+ { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
+ .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
REGINFO_SENTINEL
};
@@ -1795,9 +1800,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn,
uint32_t val)
goto bad_reg;
}
break;
- case 10: /* MMU TLB lockdown. */
- /* ??? TLB lockdown not implemented. */
- break;
case 12: /* Reserved. */
goto bad_reg;
case 15: /* Implementation specific. */
@@ -2075,9 +2077,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
goto bad_reg;
}
break;
- case 10: /* MMU TLB lockdown. */
- /* ??? TLB lockdown not implemented. */
- return 0;
case 11: /* TCM DMA control. */
case 12: /* Reserved. */
goto bad_reg;
--
1.7.1
- [Qemu-devel] [PATCH 04/33] hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs, (continued)
- [Qemu-devel] [PATCH 04/33] hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 20/33] target-arm: Convert cp15 MMU TLB control, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 25/33] target-arm: Convert cp15 crn=1 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 06/33] target-arm: Remove old cpu_arm_set_cp_io infrastructure, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 29/33] target-arm: Convert final ID registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 15/33] target-arm: Convert MMU fault status cp15 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 12/33] target-arm: Convert performance monitor registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 11/33] target-arm: Convert TLS registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 07/33] target-arm: Add register_cp_regs_for_features(), Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 01/33] target-arm: Fix 11MPCore cache type register value, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 18/33] target-arm: Convert cp15 crn=10 registers,
Peter Maydell <=
- [Qemu-devel] [PATCH 21/33] target-arm: Convert cp15 VA-PA translation registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 24/33] target-arm: Convert cp15 crn=9 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 23/33] target-arm: Convert cp15 crn=6 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 27/33] target-arm: Convert cp15 cache ID registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 05/33] hw/pxa2xx_pic: Convert coprocessor registers to new scheme, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 17/33] target-arm: Convert cp15 crn=13 registers, Peter Maydell, 2012/06/20
- [Qemu-devel] [PATCH 33/33] target-arm: Remove ARM_CPUID_* macros, Peter Maydell, 2012/06/20
- Re: [Qemu-devel] [PULL 00/33] target-arm queue, Blue Swirl, 2012/06/24