[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] Keeping a secondary CPU in reset

From: Thierry Reding
Subject: [Qemu-devel] Keeping a secondary CPU in reset
Date: Tue, 17 Jul 2012 07:15:24 +0200
User-agent: Mutt/1.5.21 (2010-09-15)


I've been toying around with adding NVIDIA Tegra support to QEMU. While
adding SMP support I came across a problem: on Tegra, the secondary CPU
is kept in reset by the clock-and-reset controller (CRC). When bringing
up the secondary CPU, the OS writes a given register in the CRC to
release the CPU, after which it starts running. Other hardware blocks
can also be reset by writing other registers in the CRC.

QEMU however seems to assume that all CPUs can immediately be run, so I
solved this by providing some SMP boot code that basically just executes
the wfi (wait for interrupt) instruction and raise an interrupt after
the CRC register has been written to emulate this behaviour. This is at
best kludgy, so I wonder if QEMU provides functionality that I could use
to model this properly. I didn't find any, so I wonder if it might be a
good idea to add some kind of generic reset framework.


Attachment: pgp0DL8YfI8oX.pgp
Description: PGP signature

reply via email to

[Prev in Thread] Current Thread [Next in Thread]