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Re: [Qemu-devel] [PATCH v7 12/14] target-mips-ase-dsp: Add MIPS DSP proc
From: |
Jia Liu |
Subject: |
Re: [Qemu-devel] [PATCH v7 12/14] target-mips-ase-dsp: Add MIPS DSP processors |
Date: |
Sat, 8 Sep 2012 20:01:30 +0800 |
Hi Aurelien,
On Thu, Sep 6, 2012 at 5:11 PM, Aurelien Jarno <address@hidden> wrote:
> On Tue, Aug 28, 2012 at 02:36:23PM +0800, Jia Liu wrote:
>> Add MIPS[32|64] ASE DSP[R1|R2] generic cpu model for test.
>>
>> Signed-off-by: Jia Liu <address@hidden>
>> ---
>> target-mips/translate_init.c | 55
>> ++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 55 insertions(+)
>>
>> diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
>> index c39138f..65ba547 100644
>> --- a/target-mips/translate_init.c
>> +++ b/target-mips/translate_init.c
>> @@ -311,6 +311,32 @@ static const mips_def_t mips_defs[] =
>> .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
>> .mmu_type = MMU_TYPE_R4000,
>> },
>> + {
>> + /* A generic CPU providing MIPS32 ASE DSP Release 2 features.
>> + FIXME: Eventually this should be replaced by a real CPU model. */
>
> Is it something that could be fixed now? I guess MIPS produces core with
> this instruction set.
>
I'll make it 74kf. Is it OK?
>> + .name = "mips32dspr2",
>> + .CP0_PRid = 0x00019300,
>> + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
>> + (MMU_TYPE_R4000 << CP0C0_MT),
>> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
>> + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
>> + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
>> + (1 << CP0C1_CA),
>> + .CP0_Config2 = MIPS_CONFIG2,
>> + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP),
>> + .CP0_LLAddr_rw_bitmask = 0,
>> + .CP0_LLAddr_shift = 4,
>> + .SYNCI_Step = 32,
>> + .CCRes = 2,
>> + /* No DSP implemented. */
>> + .CP0_Status_rw_bitmask = 0x3778FF1F,
>> + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
>> + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
>> + .SEGBITS = 32,
>> + .PABITS = 32,
>> + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
>> + .mmu_type = MMU_TYPE_R4000,
>> + },
>> #if defined(TARGET_MIPS64)
>> {
>> .name = "R4000",
>> @@ -484,6 +510,35 @@ static const mips_def_t mips_defs[] =
>> .insn_flags = CPU_LOONGSON2F,
>> .mmu_type = MMU_TYPE_R4000,
>> },
>> + {
>> + /* A generic CPU providing MIPS64 ASE DSP Release 2 features.
>> + FIXME: Eventually this should be replaced by a real CPU model. */
>> + .name = "mips64dspr2",
>> + /* We emulate a later version of the 20Kc, earlier ones had a broken
>> + WAIT instruction. */
>> + .CP0_PRid = 0x000182a0,
>> + .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
>> + (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
>> + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
>> + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
>> + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
>> + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
>> + .CP0_Config2 = MIPS_CONFIG2,
>> + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP),
>> + .CP0_LLAddr_rw_bitmask = 0,
>> + .CP0_LLAddr_shift = 0,
>> + .SYNCI_Step = 32,
>> + .CCRes = 1,
>> + .CP0_Status_rw_bitmask = 0x37FBFFFF,
>> + /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
>> + .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
>> + (1 << FCR0_D) | (1 << FCR0_S) |
>> + (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
>> + .SEGBITS = 40,
>> + .PABITS = 36,
>> + .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
>> + .mmu_type = MMU_TYPE_R4000,
>> + },
>>
>> #endif
>> };
>> --
>> 1.7.9.5
>>
>>
>
> --
> Aurelien Jarno GPG: 1024D/F1BCDB73
> address@hidden http://www.aurel32.net
Regards,
Jia