[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 0/9] target-xtensa: implement FP coprocessor option
From: |
Max Filippov |
Subject: |
[Qemu-devel] [PATCH 0/9] target-xtensa: implement FP coprocessor option |
Date: |
Sun, 9 Sep 2012 05:29:49 +0400 |
This series implements floating point coprocessor and coprocessor context
options for xtensa and fixes a couple of bugs to make it work.
Max Filippov (9):
softfloat: make float_muladd_negate_* flags independent
target-xtensa: handle boolean option in overlays
target-xtensa: specialize softfloat NaN rules
target-xtensa: add FP registers
target-xtensa: implement LSCX and LSCI groups
target-xtensa: implement FP0 arithmetic
target-xtensa: implement FP0 conversions
target-xtensa: implement FP1 group
target-xtensa: implement coprocessor context option
fpu/softfloat-specialize.h | 9 +-
fpu/softfloat.h | 2 +-
gdbstub.c | 8 +
target-xtensa/cpu.h | 8 +
target-xtensa/helper.h | 21 +++
target-xtensa/op_helper.c | 140 +++++++++++++++++
target-xtensa/overlay_tool.h | 1 +
target-xtensa/translate.c | 337 ++++++++++++++++++++++++++++++++++++++++--
8 files changed, 510 insertions(+), 16 deletions(-)
--
1.7.7.6
- [Qemu-devel] [PATCH 0/9] target-xtensa: implement FP coprocessor option,
Max Filippov <=
[Qemu-devel] [PATCH 4/9] target-xtensa: add FP registers, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 5/9] target-xtensa: implement LSCX and LSCI groups, Max Filippov, 2012/09/08