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Re: [Qemu-devel] [PATCH 6/9] target-xtensa: implement FP0 arithmetic
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 6/9] target-xtensa: implement FP0 arithmetic |
Date: |
Sun, 9 Sep 2012 13:56:42 +0100 |
On 9 September 2012 13:25, Max Filippov <address@hidden> wrote:
> On Sun, Sep 9, 2012 at 2:05 PM, Peter Maydell <address@hidden> wrote:
>> Given that these are just 'v &= 0x7fffffff' and 'v ^= 0x80000000'
>> it seems like it would be better to just generate code for them
>> rather than calling out to a helper, though in some ways it does
>> break the abstraction layer of the softfloat library. I've been
>> toying with the idea of doing this for target-arm.
>
> I doubt that these opcodes are used often enough to justify such
> hack.
>
>> (we could have gen_float32_abs() and gen_float32_chs() in
>> softfloat.h, or would that be a worse layering violation in
>> the other direction? I dunno.)
>
> IMHO this approach is a bit cleaner.
Mmm, maybe. I think you can reasonably leave your patch as it is,
anyway.
-- PMM
- [Qemu-devel] [PATCH 3/9] target-xtensa: specialize softfloat NaN rules, (continued)
[Qemu-devel] [PATCH 4/9] target-xtensa: add FP registers, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 5/9] target-xtensa: implement LSCX and LSCI groups, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 6/9] target-xtensa: implement FP0 arithmetic, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 7/9] target-xtensa: implement FP0 conversions, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 8/9] target-xtensa: implement FP1 group, Max Filippov, 2012/09/08
[Qemu-devel] [PATCH 9/9] target-xtensa: implement coprocessor context option, Max Filippov, 2012/09/08