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Re: [Qemu-devel] [PATCH v2 08/10] target-xtensa: implement FP0 conversio
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 08/10] target-xtensa: implement FP0 conversions |
Date: |
Sun, 9 Sep 2012 17:16:09 +0100 |
On 9 September 2012 17:04, Max Filippov <address@hidden> wrote:
> These are FP to integer and integer to FP conversion opcodes.
> See ISA, 4.3.10 for more details.
>
> Note that utrunc.s implementation follows ISS behaviour, not ISA.
ISS here means "instruction set simulator", right? Do you
have any actual silicon you can check behaviour against?
Basically there are three votes here (documentation, simulator
and silicon) and QEMU should follow the majority opinion in
the absence of any more official word.
-- PMM
- [Qemu-devel] [PATCH v2 00/10] target-xtensa: implement FP coprocessor option, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 01/10] softfloat: make float_muladd_negate_* flags independent, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 02/10] softfloat: add NO_SIGNALING_NANS, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 03/10] target-xtensa: handle boolean option in overlays, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 04/10] target-xtensa: specialize softfloat NaN rules, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 05/10] target-xtensa: add FP registers, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 06/10] target-xtensa: implement LSCX and LSCI groups, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 07/10] target-xtensa: implement FP0 arithmetic, Max Filippov, 2012/09/09
- [Qemu-devel] [PATCH v2 08/10] target-xtensa: implement FP0 conversions, Max Filippov, 2012/09/09
[Qemu-devel] [PATCH v2 09/10] target-xtensa: implement FP1 group, Max Filippov, 2012/09/09
[Qemu-devel] [PATCH v2 10/10] target-xtensa: implement coprocessor context option, Max Filippov, 2012/09/09