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Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level al
From: |
Jan Kiszka |
Subject: |
Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request |
Date: |
Tue, 11 Sep 2012 11:05:53 +0200 |
User-agent: |
Mozilla/5.0 (X11; U; Linux i686 (x86_64); de; rv:1.8.1.12) Gecko/20080226 SUSE/2.0.0.12-1.1 Thunderbird/2.0.0.12 Mnenhy/0.7.5.666 |
On 2012-09-11 06:32, Matthew Ogilvie wrote:
> On Mon, Sep 10, 2012 at 11:09:27AM +0200, Jan Kiszka wrote:
>> On 2012-09-10 10:56, Avi Kivity wrote:
>>> On 09/10/2012 04:27 AM, Matthew Ogilvie wrote:
>>>> Intel's definition of "edge triggered" means: "asserted with a
>>>> low-to-high transition at the time an interrupt is registered and
>>>> then kept high until the interrupt is served via one of the
>>>> EOI mechanisms or goes away unhandled."
>>>>
>>>> So the only difference between edge triggered and level triggered
>>>> is in the leading edge, with no difference in the trailing edge.
>>>
>>> Hard to believe. So an edge while cpu interrupts are disabled is ignored?
>>
>> No, this is about the PIC, not the CPU interrupt inputs.
>>
>> Matthew, did you verify this on real hardware by reading back the IRR as
>> I suggested?
>>
>> Jan
>
> I hadn't before, but now that I've checked, it's as expected:
>
> -----------
> Real hardware [Pentium 4]:
>
> cmdRead unmask IRR=4005 mask IRR=4001 sti unmask irq14 IRR=0001 DONE
>
> [I also see a final IRR=0000 occasionally. Probably just happened to
> ask it while the timer (IRQ0) line is low (without the new understanding
> of the trailing edge of an edge triggered interrupt, this would
> have been confusing). I have most IRQ's (including
> timer) masked off.]
>
> -----------
> Unpatched qemu:
>
> cmdRead unmask IRR=4015 mask IRR=4015 sti irq15 unmask IRR=4015 DONE
>
> [Presumably IRQ4 (0x10 - qemu's serial device model?) had a transient
> edge during initialization, but had been masked off even before I
> masked it off?]
>
> -----------
> Patched qemu:
>
> cmdRead unmask IRR=4005 mask IRR=4001 sti unmask irq14 IRR=0001 DONE
>
I think this is convincing, maybe worth documenting in the related
changelogs of QEMU and KVM. Avi, doubts remaining?
Jan
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- [Qemu-devel] [PATCH v5 4/6] vga: add some optional CGA compatibility hacks, (continued)
- [Qemu-devel] [PATCH v5 4/6] vga: add some optional CGA compatibility hacks, Matthew Ogilvie, 2012/09/09
- [Qemu-devel] [PATCH v5 6/6] i8259: refactor pic_set_irq level logic, Matthew Ogilvie, 2012/09/09
- [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Matthew Ogilvie, 2012/09/09
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Avi Kivity, 2012/09/10
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Jan Kiszka, 2012/09/10
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Avi Kivity, 2012/09/10
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Jan Kiszka, 2012/09/10
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Maciej W. Rozycki, 2012/09/10
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Avi Kivity, 2012/09/11
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Matthew Ogilvie, 2012/09/11
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request,
Jan Kiszka <=
- Re: [Qemu-devel] [PATCH v5 5/6] i8259: fix so that dropping IRQ level always clears the interrupt request, Avi Kivity, 2012/09/11