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[Qemu-devel] [PATCH 7/9] VGA: Flush coalesced MMIO on related MMIO/PIO a
From: |
Marcelo Tosatti |
Subject: |
[Qemu-devel] [PATCH 7/9] VGA: Flush coalesced MMIO on related MMIO/PIO accesses |
Date: |
Tue, 11 Sep 2012 18:26:35 -0300 |
From: Jan Kiszka <address@hidden>
In preparation of stopping to flush coalesced MMIO unconditionally on
vmexits, mark VGA MMIO and PIO regions as synchronous /wrt coalesced
MMIO and flush the buffer explicitly on PIO accesses that do not use
generic memory regions yet.
Signed-off-by: Jan Kiszka <address@hidden>
Signed-off-by: Marcelo Tosatti <address@hidden>
---
hw/cirrus_vga.c | 7 +++++++
hw/qxl.c | 1 +
hw/vga-isa-mm.c | 1 +
hw/vga.c | 5 +++++
hw/vmware_vga.c | 1 +
5 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c
index e8dcc6b..9a0a565 100644
--- a/hw/cirrus_vga.c
+++ b/hw/cirrus_vga.c
@@ -2441,6 +2441,8 @@ static uint32_t cirrus_vga_ioport_read(void *opaque,
uint32_t addr)
VGACommonState *s = &c->vga;
int val, index;
+ qemu_flush_coalesced_mmio_buffer();
+
if (vga_ioport_invalid(s, addr)) {
val = 0xff;
} else {
@@ -2534,6 +2536,8 @@ static void cirrus_vga_ioport_write(void *opaque,
uint32_t addr, uint32_t val)
VGACommonState *s = &c->vga;
int index;
+ qemu_flush_coalesced_mmio_buffer();
+
/* check port range access depending on color/monochrome mode */
if (vga_ioport_invalid(s, addr)) {
return;
@@ -2854,6 +2858,7 @@ static void cirrus_init_common(CirrusVGAState * s, int
device_id, int is_pci,
/* I/O handler for LFB */
memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s,
"cirrus-linear-io", VGA_RAM_SIZE);
+ memory_region_set_flush_coalesced(&s->cirrus_linear_io);
/* I/O handler for LFB */
memory_region_init_io(&s->cirrus_linear_bitblt_io,
@@ -2861,10 +2866,12 @@ static void cirrus_init_common(CirrusVGAState * s, int
device_id, int is_pci,
s,
"cirrus-bitblt-mmio",
0x400000);
+ memory_region_set_flush_coalesced(&s->cirrus_linear_bitblt_io);
/* I/O handler for memory-mapped I/O */
memory_region_init_io(&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s,
"cirrus-mmio", CIRRUS_PNPMMIO_SIZE);
+ memory_region_set_flush_coalesced(&s->cirrus_mmio_io);
s->real_vram_size =
(s->device_id == CIRRUS_ID_CLGD5446) ? 4096 * 1024 : 2048 * 1024;
diff --git a/hw/qxl.c b/hw/qxl.c
index 5b3f484..43d6a67 100644
--- a/hw/qxl.c
+++ b/hw/qxl.c
@@ -1910,6 +1910,7 @@ static int qxl_init_common(PCIQXLDevice *qxl)
if (qxl->id == 0) {
vga_dirty_log_start(&qxl->vga);
}
+ memory_region_set_flush_coalesced(&qxl->io_bar);
pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
diff --git a/hw/vga-isa-mm.c b/hw/vga-isa-mm.c
index 44ae7d9..306e6ba 100644
--- a/hw/vga-isa-mm.c
+++ b/hw/vga-isa-mm.c
@@ -107,6 +107,7 @@ static void vga_mm_init(ISAVGAMMState *s,
target_phys_addr_t vram_base,
s_ioport_ctrl = g_malloc(sizeof(*s_ioport_ctrl));
memory_region_init_io(s_ioport_ctrl, &vga_mm_ctrl_ops, s,
"vga-mm-ctrl", 0x100000);
+ memory_region_set_flush_coalesced(s_ioport_ctrl);
vga_io_memory = g_malloc(sizeof(*vga_io_memory));
/* XXX: endianness? */
diff --git a/hw/vga.c b/hw/vga.c
index 80299ea..afaef0d 100644
--- a/hw/vga.c
+++ b/hw/vga.c
@@ -361,6 +361,8 @@ uint32_t vga_ioport_read(void *opaque, uint32_t addr)
VGACommonState *s = opaque;
int val, index;
+ qemu_flush_coalesced_mmio_buffer();
+
if (vga_ioport_invalid(s, addr)) {
val = 0xff;
} else {
@@ -453,6 +455,8 @@ void vga_ioport_write(void *opaque, uint32_t addr, uint32_t
val)
VGACommonState *s = opaque;
int index;
+ qemu_flush_coalesced_mmio_buffer();
+
/* check port range access depending on color/monochrome mode */
if (vga_ioport_invalid(s, addr)) {
return;
@@ -2338,6 +2342,7 @@ MemoryRegion *vga_init_io(VGACommonState *s,
vga_mem = g_malloc(sizeof(*vga_mem));
memory_region_init_io(vga_mem, &vga_mem_ops, s,
"vga-lowmem", 0x20000);
+ memory_region_set_flush_coalesced(vga_mem);
return vga_mem;
}
diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index b68e883..e815a04 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -1186,6 +1186,7 @@ static int pci_vmsvga_initfn(PCIDevice *dev)
memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip,
"vmsvga-io", 0x10);
+ memory_region_set_flush_coalesced(&s->io_bar);
pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
vmsvga_init(&s->chip, pci_address_space(dev),
--
1.7.6.4
- [Qemu-devel] [PATCH 0/9] [PULL] qemu-kvm.git uq/master queue, Marcelo Tosatti, 2012/09/11
- [Qemu-devel] [PATCH 3/9] memory: Flush coalesced MMIO on selected region access, Marcelo Tosatti, 2012/09/11
- [Qemu-devel] [PATCH 2/9] kvm-all.c: Move init of irqchip_inject_ioctl out of kvm_irqchip_create(), Marcelo Tosatti, 2012/09/11
- [Qemu-devel] [PATCH 7/9] VGA: Flush coalesced MMIO on related MMIO/PIO accesses,
Marcelo Tosatti <=
- [Qemu-devel] [PATCH 9/9] kvm: Rename irqchip_inject_ioctl to irq_set_ioctl, Marcelo Tosatti, 2012/09/11
- [Qemu-devel] [PATCH 5/9] memory: Fold memory_region_update_topology into memory_region_transaction_commit, Marcelo Tosatti, 2012/09/11
- [Qemu-devel] [PATCH 1/9] update-linux-headers.sh: Don't hard code list of architectures, Marcelo Tosatti, 2012/09/11
- [Qemu-devel] [PATCH 8/9] kvm: Stop flushing coalesced MMIO on vmexit, Marcelo Tosatti, 2012/09/11
- [Qemu-devel] [PATCH 6/9] memory: Flush coalesced MMIO on mapping and state changes, Marcelo Tosatti, 2012/09/11
- [Qemu-devel] [PATCH 4/9] memory: Use transaction_begin/commit also for single-step operations, Marcelo Tosatti, 2012/09/11
- Re: [Qemu-devel] [PATCH 0/9] [PULL] qemu-kvm.git uq/master queue, Anthony Liguori, 2012/09/17