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Re: [Qemu-devel] [PATCH 1/7] target-mips: Set opn in gen_ldst_multiple.
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH 1/7] target-mips: Set opn in gen_ldst_multiple. |
Date: |
Tue, 18 Sep 2012 18:38:32 +0200 |
User-agent: |
Mutt/1.5.21 (2010-09-15) |
On Mon, Sep 17, 2012 at 02:35:07PM -0700, Richard Henderson wrote:
> Used by MIPS_DEBUG, when enabled.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target-mips/translate.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 52eeb2b..50153a9 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -9855,6 +9855,7 @@ static void gen_andi16 (CPUMIPSState *env, DisasContext
> *ctx)
> static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist,
> int base, int16_t offset)
> {
> + const char *opn = "ldst_multiple";
> TCGv t0, t1;
> TCGv_i32 t2;
>
> @@ -9874,19 +9875,24 @@ static void gen_ldst_multiple (DisasContext *ctx,
> uint32_t opc, int reglist,
> switch (opc) {
> case LWM32:
> gen_helper_lwm(cpu_env, t0, t1, t2);
> + opn = "lwm";
> break;
> case SWM32:
> gen_helper_swm(cpu_env, t0, t1, t2);
> + opn = "swm";
> break;
> #ifdef TARGET_MIPS64
> case LDM:
> gen_helper_ldm(cpu_env, t0, t1, t2);
> + opn = "ldm";
> break;
> case SDM:
> gen_helper_sdm(cpu_env, t0, t1, t2);
> + opn = "sdm";
> break;
> #endif
> }
> + (void)opn;
> MIPS_DEBUG("%s, %x, %d(%s)", opn, reglist, offset, regnames[base]);
> tcg_temp_free(t0);
> tcg_temp_free(t1);
> --
> 1.7.11.4
>
Looks fine to me.
Acked-by: Aurelien Jarno <address@hidden>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH v2 0/7] target-mips improvements, Richard Henderson, 2012/09/17
- [Qemu-devel] [PATCH 1/7] target-mips: Set opn in gen_ldst_multiple., Richard Henderson, 2012/09/17
- Re: [Qemu-devel] [PATCH 1/7] target-mips: Set opn in gen_ldst_multiple.,
Aurelien Jarno <=
- [Qemu-devel] [PATCH 2/7] target-mips: Fix MIPS_DEBUG., Richard Henderson, 2012/09/17
- [Qemu-devel] [PATCH 3/7] target-mips: Always evaluate debugging macro arguments, Richard Henderson, 2012/09/17
- [Qemu-devel] [PATCH 5/7] target-mips: Use TCG registers for the FPU., Richard Henderson, 2012/09/17
- [Qemu-devel] [PATCH 6/7] target-mips: Add accessors for the two 32-bit halves of a 64-bit FPR, Richard Henderson, 2012/09/17
- [Qemu-devel] [PATCH 7/7] target-mips: Implement Loongson Multimedia Instructions, Richard Henderson, 2012/09/17
- [Qemu-devel] [PATCH 4/7] target-mips: Pass DisasContext to fpr32 load/store routines, Richard Henderson, 2012/09/17