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Re: [Qemu-devel] [PATCH 3/7] tcg-i386: Implement movcond
From: |
Alex Barcelo |
Subject: |
Re: [Qemu-devel] [PATCH 3/7] tcg-i386: Implement movcond |
Date: |
Mon, 24 Sep 2012 23:37:54 +0200 |
just finished a git-bisect and I found this... and now I do not fully
understand why I have the problem.
To replicate the error (in a i386 machine, at least):
$ make clean && ./configure --enable-debug && make -j && make install
[Note: I tried both ppc and i386 targets, so doesn't seem machine-dependent]
$ ./path/to/qemu/bin/qemu-i386 doesntmatter
Invalid op definition for movcond_i32
/mnt/DATA/DARCO/qemu-git/tcg/tcg.c:1170: tcg fatal error
Aborted
"doesntmatter" can be a non-existing file, or an existing file. It
seems to fail before checking file existence.
On Fri, Sep 21, 2012 at 7:13 PM, Richard Henderson <address@hidden> wrote:
> Signed-off-by: Richard Henderson <address@hidden>
> Reviewed-by: Aurelien Jarno <address@hidden>
> ---
> tcg/i386/tcg-target.c | 29 +++++++++++++++++++++++++++++
> tcg/i386/tcg-target.h | 7 ++++++-
> 2 files changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
> index 3017858..aa1fa9f 100644
> --- a/tcg/i386/tcg-target.c
> +++ b/tcg/i386/tcg-target.c
> @@ -249,6 +249,7 @@ static inline int tcg_target_const_match(tcg_target_long
> val,
> #define OPC_ADD_GvEv (OPC_ARITH_GvEv | (ARITH_ADD << 3))
> #define OPC_BSWAP (0xc8 | P_EXT)
> #define OPC_CALL_Jz (0xe8)
> +#define OPC_CMOVCC (0x40 | P_EXT) /* ... plus condition code */
> #define OPC_CMP_GvEv (OPC_ARITH_GvEv | (ARITH_CMP << 3))
> #define OPC_DEC_r32 (0x48)
> #define OPC_IMUL_GvEv (0xaf | P_EXT)
> @@ -936,6 +937,24 @@ static void tcg_out_setcond2(TCGContext *s, const TCGArg
> *args,
> }
> #endif
>
> +static void tcg_out_movcond32(TCGContext *s, TCGCond cond, TCGArg dest,
> + TCGArg c1, TCGArg c2, int const_c2,
> + TCGArg v1)
> +{
> + tcg_out_cmp(s, c1, c2, const_c2, 0);
> + tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond], dest, v1);
> +}
> +
> +#if TCG_TARGET_REG_BITS == 64
> +static void tcg_out_movcond64(TCGContext *s, TCGCond cond, TCGArg dest,
> + TCGArg c1, TCGArg c2, int const_c2,
> + TCGArg v1)
> +{
> + tcg_out_cmp(s, c1, c2, const_c2, P_REXW);
> + tcg_out_modrm(s, OPC_CMOVCC | tcg_cond_to_jcc[cond] | P_REXW, dest, v1);
> +}
> +#endif
> +
> static void tcg_out_branch(TCGContext *s, int call, tcg_target_long dest)
> {
> tcg_target_long disp = dest - (tcg_target_long)s->code_ptr - 5;
> @@ -1668,6 +1687,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
> opc,
> tcg_out_setcond32(s, args[3], args[0], args[1],
> args[2], const_args[2]);
> break;
> + case INDEX_op_movcond_i32:
> + tcg_out_movcond32(s, args[5], args[0], args[1],
> + args[2], const_args[2], args[3]);
> + break;
>
> OP_32_64(bswap16):
> tcg_out_rolw_8(s, args[0]);
> @@ -1796,6 +1819,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
> opc,
> tcg_out_setcond64(s, args[3], args[0], args[1],
> args[2], const_args[2]);
> break;
> + case INDEX_op_movcond_i64:
> + tcg_out_movcond64(s, args[5], args[0], args[1],
> + args[2], const_args[2], args[3]);
> + break;
>
> case INDEX_op_bswap64_i64:
> tcg_out_bswap64(s, args[0]);
> @@ -1880,6 +1907,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
> { INDEX_op_setcond_i32, { "q", "r", "ri" } },
>
> { INDEX_op_deposit_i32, { "Q", "0", "Q" } },
> + { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "0" } },
>
> #if TCG_TARGET_REG_BITS == 32
> { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
> @@ -1934,6 +1962,7 @@ static const TCGTargetOpDef x86_op_defs[] = {
> { INDEX_op_ext32u_i64, { "r", "r" } },
>
> { INDEX_op_deposit_i64, { "Q", "0", "Q" } },
> + { INDEX_op_movcond_i64, { "r", "r", "re", "r", "0" } },
> #endif
>
> #if TCG_TARGET_REG_BITS == 64
> diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
> index 504f953..b356d76 100644
> --- a/tcg/i386/tcg-target.h
> +++ b/tcg/i386/tcg-target.h
> @@ -86,7 +86,12 @@ typedef enum {
> #define TCG_TARGET_HAS_nand_i32 0
> #define TCG_TARGET_HAS_nor_i32 0
> #define TCG_TARGET_HAS_deposit_i32 1
> +#if defined(__x86_64__) || defined(__i686__)
> +/* Use cmov only if the compiler is already doing so. */
> +#define TCG_TARGET_HAS_movcond_i32 1
> +#else
> #define TCG_TARGET_HAS_movcond_i32 0
> +#endif
>
> #if TCG_TARGET_REG_BITS == 64
> #define TCG_TARGET_HAS_div2_i64 1
> @@ -108,7 +113,7 @@ typedef enum {
> #define TCG_TARGET_HAS_nand_i64 0
> #define TCG_TARGET_HAS_nor_i64 0
> #define TCG_TARGET_HAS_deposit_i64 1
> -#define TCG_TARGET_HAS_movcond_i64 0
> +#define TCG_TARGET_HAS_movcond_i64 1
> #endif
>
> #define TCG_TARGET_deposit_i32_valid(ofs, len) \
> --
> 1.7.11.4
>
>
[Qemu-devel] [PATCH 2/7] target-alpha: Use movcond, Richard Henderson, 2012/09/21
[Qemu-devel] [PATCH 5/7] tcg: Optimize two-address commutative operations, Richard Henderson, 2012/09/21
[Qemu-devel] [PATCH 6/7] tcg: Streamline movcond_i64 using 32-bit arithmetic, Richard Henderson, 2012/09/21