Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/4] target-ppc: Extend FPU state for newer POWER CPUs

[Alexander Graf]

On 09.10.2012, at 13:38, Alexander Graf wrote:

> 
> On 09.10.2012, at 06:17, David Gibson wrote:
> 
>> This patch adds some extra FPU state to CPUPPCState.  Specifically,
>> fpscr is extended to a target_ulong bits, since some recent (64 bit)
>> CPUs now have more status bits than fit inside 32 bits.  Also, we add
>> the 32 VSR registers present on CPUs with VSX (these extend the
>> standard FP regs, which together with the Altivec/VMX registers form a
>> 64 x 128bit register file for VSX).
>> 
>> We don't actually support the instructions using these extra registers
>> in TCG yet, but we still need a place to store the state so we can
>> sync it with KVM and savevm/loadvm it.  This patch updates the savevm
>> code to not fail on the extended state, but also does not actually
>> save it - that's a project for another patch.
>> 
>> Signed-off-by: David Gibson <address@hidden>
>> ---
>> 
>> v2:
>> * Used target_ulong instead of uint64_t, since the extended state is used
>> only on ppc64 targets.
>> * Fixed the TCG mapping of fpscr to match the new type.
>> ---
>> target-ppc/cpu.h       |    4 +++-
>> target-ppc/machine.c   |    8 ++++++--
>> target-ppc/translate.c |    4 ++--
>> 3 files changed, 11 insertions(+), 5 deletions(-)
>> 
>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
>> index faf4404..7627722 100644
>> --- a/target-ppc/cpu.h
>> +++ b/target-ppc/cpu.h
>> @@ -963,7 +963,7 @@ struct CPUPPCState {
>>    /* floating point registers */
>>    float64 fpr[32];
>>    /* floating point status and control register */
>> -    uint32_t fpscr;
>> +    target_ulong fpscr;
> 
> This will still break TCG for qemu-system-ppc64, no?

To be more precise:

address@hidden:/home/agraf/release/qemu> grep -R cpu_fpscr target-ppc
target-ppc/translate.c:static TCGv_i32 cpu_fpscr;
target-ppc/translate.c:    cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
target-ppc/translate.c:    tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], 
cpu_fpscr, bfa);
target-ppc/translate.c:    tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << 
bfa));
target-ppc/translate.c:    tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], 
cpu_fpscr);
target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, 
FPSCR_OX);
target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, 
FPSCR_OX);
target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, 
FPSCR_OX);
target-ppc/translate.c:        tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, 
FPSCR_OX);

All those functions assume cpu_fpscr is a TCGv32. They need to be adjusted to 
work on tl instead.

Please test compile your code with configure --enable-tcg-debug.


Alex