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[Qemu-devel] [PATCH v3 11/26] tcg: fix some op flags
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v3 11/26] tcg: fix some op flags |
Date: |
Fri, 19 Oct 2012 23:39:00 +0200 |
Some branch related ops are marked with TCG_OPF_SIDE_EFFECTS, some other
not. In practice they don't need to, as they are all marked with
TCG_OPF_BB_END, which is handled specifically in all the code.
The call op is marked as TCG_OPF_SIDE_EFFECTS, which might be not true
as there is are specific flags (TCG_CALL_CONST and TCG_CALL_PURE) for
specifying that. On the other hand it always clobber arguments, so mark
it as such even if the call op is handled in a different code path.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
tcg/tcg-opc.h | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 04cb7ca..2072281 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -37,8 +37,8 @@ DEF(nopn, 0, 0, 1, 0) /* variable number of parameters */
DEF(discard, 1, 0, 0, 0)
DEF(set_label, 0, 0, 1, TCG_OPF_BB_END)
-DEF(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */
-DEF(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
+DEF(call, 0, 1, 2, TCG_OPF_CALL_CLOBBER) /* variable number of parameters */
+DEF(br, 0, 0, 1, TCG_OPF_BB_END)
#define IMPL(X) (X ? 0 : TCG_OPF_NOT_PRESENT)
#if TCG_TARGET_REG_BITS == 32
@@ -81,12 +81,11 @@ DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
-DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
+DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS == 32))
DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_REG_BITS == 32))
-DEF(brcond2_i32, 0, 4, 2,
- TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS | IMPL(TCG_TARGET_REG_BITS == 32))
+DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_REG_BITS == 32))
DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
@@ -141,7 +140,7 @@ DEF(rotl_i64, 1, 2, 0, IMPL64 |
IMPL(TCG_TARGET_HAS_rot_i64))
DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
-DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS | IMPL64)
+DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
@@ -165,8 +164,8 @@ DEF(debug_insn_start, 0, 0, 2, 0)
#else
DEF(debug_insn_start, 0, 0, 1, 0)
#endif
-DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
-DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS)
+DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
+DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
/* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
constants must be defined */
#if TCG_TARGET_REG_BITS == 32
--
1.7.10.4
- [Qemu-devel] [PATCH v3 00/26] tcg: rework liveness analysis and register allocator, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 02/26] tcg: add tcg_reg_sync(), Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 01/26] tcg: add temp_dead(), Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 23/26] target-sh4: rename helper flags, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 18/26] target-i386: rename helper flags, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 05/26] tcg: rework liveness analysis, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 11/26] tcg: fix some op flags,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v3 25/26] target-xtensa: rename helper flags, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 09/26] tcg: start with local temps in TEMP_VAL_MEM state, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 17/26] target-cris: rename helper flags, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 21/26] target-ppc: rename helper flags, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 06/26] tcg: improve tcg_reg_alloc_movi(), Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 15/26] target-alpha: rename helper flags, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 24/26] target-sparc: rename helper flags, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH 07/26] tcg: rewrite tcg_reg_alloc_mov(), Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 20/26] target-mips: rename helper flags, Aurelien Jarno, 2012/10/19
- [Qemu-devel] [PATCH v3 26/26] tcg: remove compatiblity call flags, Aurelien Jarno, 2012/10/19