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[Qemu-devel] [PATCH 08/37] target-i386: define static properties for cpu
From: |
Igor Mammedov |
Subject: |
[Qemu-devel] [PATCH 08/37] target-i386: define static properties for cpuid features |
Date: |
Mon, 22 Oct 2012 17:02:54 +0200 |
- static properties names of CPUID features are changed to have "f-" prefix,
so that it would be easy to distinguish them from other properties.
- use X86CPU as a type to count of offset correctly, because env field isn't
starting at CPUstate begining, but located after it.
Signed-off-by: Igor Mammedov <address@hidden>
---
target-i386/cpu.c | 112 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 112 insertions(+)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 63ea74b..dbf2be7 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -33,6 +33,7 @@
#include "hyperv.h"
#include "hw/hw.h"
+#include "hw/qdev-properties.h"
#if defined(CONFIG_KVM)
#include <linux/kvm_para.h>
#endif
@@ -111,6 +112,115 @@ static const char *cpuid_7_0_ebx_feature_name[] = {
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
};
+static Property cpu_x86_properties[] = {
+ DEFINE_PROP_BIT("f-fpu", X86CPU, env.cpuid_features, 0, false),
+ DEFINE_PROP_BIT("f-vme", X86CPU, env.cpuid_features, 1, false),
+ DEFINE_PROP_BIT("f-de", X86CPU, env.cpuid_features, 2, false),
+ DEFINE_PROP_BIT("f-pse", X86CPU, env.cpuid_features, 3, false),
+ DEFINE_PROP_BIT("f-tsc", X86CPU, env.cpuid_features, 4, false),
+ DEFINE_PROP_BIT("f-msr", X86CPU, env.cpuid_features, 5, false),
+ DEFINE_PROP_BIT("f-pae", X86CPU, env.cpuid_features, 6, false),
+ DEFINE_PROP_BIT("f-mce", X86CPU, env.cpuid_features, 7, false),
+ DEFINE_PROP_BIT("f-cx8", X86CPU, env.cpuid_features, 8, false),
+ DEFINE_PROP_BIT("f-apic", X86CPU, env.cpuid_features, 9, false),
+ DEFINE_PROP_BIT("f-sep", X86CPU, env.cpuid_features, 11, false),
+ DEFINE_PROP_BIT("f-mtrr", X86CPU, env.cpuid_features, 12, false),
+ DEFINE_PROP_BIT("f-pge", X86CPU, env.cpuid_features, 13, false),
+ DEFINE_PROP_BIT("f-mca", X86CPU, env.cpuid_features, 14, false),
+ DEFINE_PROP_BIT("f-cmov", X86CPU, env.cpuid_features, 15, false),
+ DEFINE_PROP_BIT("f-pat", X86CPU, env.cpuid_features, 16, false),
+ DEFINE_PROP_BIT("f-pse36", X86CPU, env.cpuid_features, 17, false),
+ DEFINE_PROP_BIT("f-pn" /* Intel psn */, X86CPU, env.cpuid_features, 18,
false),
+ DEFINE_PROP_BIT("f-clflush" /* Intel clfsh */, X86CPU, env.cpuid_features,
19, false),
+ DEFINE_PROP_BIT("f-ds" /* Intel dts */, X86CPU, env.cpuid_features, 21,
false),
+ DEFINE_PROP_BIT("f-acpi", X86CPU, env.cpuid_features, 22, false),
+ DEFINE_PROP_BIT("f-mmx", X86CPU, env.cpuid_features, 23, false),
+ DEFINE_PROP_BIT("f-fxsr", X86CPU, env.cpuid_features, 24, false),
+ DEFINE_PROP_BIT("f-sse", X86CPU, env.cpuid_features, 25, false),
+ DEFINE_PROP_BIT("f-sse2", X86CPU, env.cpuid_features, 26, false),
+ DEFINE_PROP_BIT("f-ss", X86CPU, env.cpuid_features, 27, false),
+ DEFINE_PROP_BIT("f-ht" /* Intel htt */, X86CPU, env.cpuid_features, 28,
false),
+ DEFINE_PROP_BIT("f-tm", X86CPU, env.cpuid_features, 29, false),
+ DEFINE_PROP_BIT("f-ia64", X86CPU, env.cpuid_features, 30, false),
+ DEFINE_PROP_BIT("f-pbe", X86CPU, env.cpuid_features, 31, false),
+ DEFINE_PROP_BIT("f-pni" /* Intel,AMD sse3 */, X86CPU,
env.cpuid_ext_features, 0, false),
+ DEFINE_PROP_BIT("f-sse3" /* Intel,AMD sse3 */, X86CPU,
env.cpuid_ext_features, 0, false),
+ DEFINE_PROP_BIT("f-pclmulqdq", X86CPU, env.cpuid_ext_features, 1, false),
+ DEFINE_PROP_BIT("f-pclmuldq", X86CPU, env.cpuid_ext_features, 1, false),
+ DEFINE_PROP_BIT("f-dtes64", X86CPU, env.cpuid_ext_features, 2, false),
+ DEFINE_PROP_BIT("f-monitor", X86CPU, env.cpuid_ext_features, 3, false),
+ DEFINE_PROP_BIT("f-ds_cpl", X86CPU, env.cpuid_ext_features, 4, false),
+ DEFINE_PROP_BIT("f-vmx", X86CPU, env.cpuid_ext_features, 5, false),
+ DEFINE_PROP_BIT("f-smx", X86CPU, env.cpuid_ext_features, 6, false),
+ DEFINE_PROP_BIT("f-est", X86CPU, env.cpuid_ext_features, 7, false),
+ DEFINE_PROP_BIT("f-tm2", X86CPU, env.cpuid_ext_features, 8, false),
+ DEFINE_PROP_BIT("f-ssse3", X86CPU, env.cpuid_ext_features, 9, false),
+ DEFINE_PROP_BIT("f-cid", X86CPU, env.cpuid_ext_features, 10, false),
+ DEFINE_PROP_BIT("f-fma", X86CPU, env.cpuid_ext_features, 12, false),
+ DEFINE_PROP_BIT("f-cx16", X86CPU, env.cpuid_ext_features, 13, false),
+ DEFINE_PROP_BIT("f-xtpr", X86CPU, env.cpuid_ext_features, 14, false),
+ DEFINE_PROP_BIT("f-pdcm", X86CPU, env.cpuid_ext_features, 15, false),
+ DEFINE_PROP_BIT("f-pcid", X86CPU, env.cpuid_ext_features, 17, false),
+ DEFINE_PROP_BIT("f-dca", X86CPU, env.cpuid_ext_features, 18, false),
+ DEFINE_PROP_BIT("f-sse4.1", X86CPU, env.cpuid_ext_features, 19, false),
+ DEFINE_PROP_BIT("f-sse4.2", X86CPU, env.cpuid_ext_features, 20, false),
+ DEFINE_PROP_BIT("f-sse4_1", X86CPU, env.cpuid_ext_features, 19, false),
+ DEFINE_PROP_BIT("f-sse4_2", X86CPU, env.cpuid_ext_features, 20, false),
+ DEFINE_PROP_BIT("f-x2apic", X86CPU, env.cpuid_ext_features, 21, false),
+ DEFINE_PROP_BIT("f-movbe", X86CPU, env.cpuid_ext_features, 22, false),
+ DEFINE_PROP_BIT("f-popcnt", X86CPU, env.cpuid_ext_features, 23, false),
+ DEFINE_PROP_BIT("f-tsc-deadline", X86CPU, env.cpuid_ext_features, 24,
false),
+ DEFINE_PROP_BIT("f-aes", X86CPU, env.cpuid_ext_features, 25, false),
+ DEFINE_PROP_BIT("f-xsave", X86CPU, env.cpuid_ext_features, 26, false),
+ DEFINE_PROP_BIT("f-osxsave", X86CPU, env.cpuid_ext_features, 27, false),
+ DEFINE_PROP_BIT("f-avx", X86CPU, env.cpuid_ext_features, 28, false),
+ DEFINE_PROP_BIT("f-hypervisor", X86CPU, env.cpuid_ext_features, 31, false),
+ DEFINE_PROP_BIT("f-syscall", X86CPU, env.cpuid_ext2_features, 11, false),
+ DEFINE_PROP_BIT("f-nx", X86CPU, env.cpuid_ext2_features, 20, false),
+ DEFINE_PROP_BIT("f-xd", X86CPU, env.cpuid_ext2_features, 20, false),
+ DEFINE_PROP_BIT("f-mmxext", X86CPU, env.cpuid_ext2_features, 22, false),
+ DEFINE_PROP_BIT("f-fxsr_opt", X86CPU, env.cpuid_ext2_features, 25, false),
+ DEFINE_PROP_BIT("f-ffxsr", X86CPU, env.cpuid_ext2_features, 25, false),
+ DEFINE_PROP_BIT("f-pdpe1gb" /* AMD Page1GB */, X86CPU,
env.cpuid_ext2_features, 26, false),
+ DEFINE_PROP_BIT("f-rdtscp", X86CPU, env.cpuid_ext2_features, 27, false),
+ DEFINE_PROP_BIT("f-lahf_lm" /* AMD LahfSahf */, X86CPU,
env.cpuid_ext3_features, 0, false),
+ DEFINE_PROP_BIT("f-cmp_legacy", X86CPU, env.cpuid_ext3_features, 1,
false),
+ DEFINE_PROP_BIT("f-svm", X86CPU, env.cpuid_ext3_features, 2, false),
+ DEFINE_PROP_BIT("f-extapic" /* AMD ExtApicSpace */, X86CPU,
env.cpuid_ext3_features, 3, false),
+ DEFINE_PROP_BIT("f-cr8legacy" /* AMD AltMovCr8 */, X86CPU,
env.cpuid_ext3_features, 4, false),
+ DEFINE_PROP_BIT("f-abm", X86CPU, env.cpuid_ext3_features, 5, false),
+ DEFINE_PROP_BIT("f-sse4a", X86CPU, env.cpuid_ext3_features, 6, false),
+ DEFINE_PROP_BIT("f-misalignsse", X86CPU, env.cpuid_ext3_features, 7,
false),
+ DEFINE_PROP_BIT("f-3dnowprefetch", X86CPU, env.cpuid_ext3_features, 8,
false),
+ DEFINE_PROP_BIT("f-osvw", X86CPU, env.cpuid_ext3_features, 9, false),
+ DEFINE_PROP_BIT("f-ibs", X86CPU, env.cpuid_ext3_features, 10, false),
+ DEFINE_PROP_BIT("f-xop", X86CPU, env.cpuid_ext3_features, 11, false),
+ DEFINE_PROP_BIT("f-skinit", X86CPU, env.cpuid_ext3_features, 12, false),
+ DEFINE_PROP_BIT("f-wdt", X86CPU, env.cpuid_ext3_features, 13, false),
+ DEFINE_PROP_BIT("f-fma4", X86CPU, env.cpuid_ext3_features, 16, false),
+ DEFINE_PROP_BIT("f-cvt16", X86CPU, env.cpuid_ext3_features, 18, false),
+ DEFINE_PROP_BIT("f-nodeid_msr", X86CPU, env.cpuid_ext3_features, 19,
false),
+ DEFINE_PROP_BIT("f-kvmclock", X86CPU, env.cpuid_kvm_features, 0, false),
+ DEFINE_PROP_BIT("f-kvm_nopiodelay", X86CPU, env.cpuid_kvm_features, 1,
false),
+ DEFINE_PROP_BIT("f-kvm_mmu", X86CPU, env.cpuid_kvm_features, 2, false),
+ DEFINE_PROP_BIT("f-kvmclock2", X86CPU, env.cpuid_kvm_features, 3, false),
+ DEFINE_PROP_BIT("f-kvm_asyncpf", X86CPU, env.cpuid_kvm_features, 4,
false),
+ DEFINE_PROP_BIT("f-kvm_pv_eoi", X86CPU, env.cpuid_kvm_features, 6, false),
+ DEFINE_PROP_BIT("f-npt", X86CPU, env.cpuid_svm_features, 0, false),
+ DEFINE_PROP_BIT("f-lbrv", X86CPU, env.cpuid_svm_features, 1, false),
+ DEFINE_PROP_BIT("f-svm_lock", X86CPU, env.cpuid_svm_features, 2, false),
+ DEFINE_PROP_BIT("f-nrip_save", X86CPU, env.cpuid_svm_features, 3, false),
+ DEFINE_PROP_BIT("f-tsc_scale", X86CPU, env.cpuid_svm_features, 4, false),
+ DEFINE_PROP_BIT("f-vmcb_clean", X86CPU, env.cpuid_svm_features, 5, false),
+ DEFINE_PROP_BIT("f-flushbyasid", X86CPU, env.cpuid_svm_features, 6,
false),
+ DEFINE_PROP_BIT("f-decodeassists", X86CPU, env.cpuid_svm_features, 7,
false),
+ DEFINE_PROP_BIT("f-pause_filter", X86CPU, env.cpuid_svm_features, 10,
false),
+ DEFINE_PROP_BIT("f-pfthreshold", X86CPU, env.cpuid_svm_features, 12,
false),
+ DEFINE_PROP_BIT("f-smep", X86CPU, env.cpuid_7_0_ebx_features, 7, false),
+ DEFINE_PROP_BIT("f-smap", X86CPU, env.cpuid_7_0_ebx_features, 20, false),
+ DEFINE_PROP_END_OF_LIST(),
+ };
+
/* collects per-function cpuid data
*/
typedef struct model_features_t {
@@ -1948,9 +2058,11 @@ static void x86_cpu_common_class_init(ObjectClass *oc,
void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
xcc->parent_reset = cc->reset;
cc->reset = x86_cpu_reset;
+ dc->props = cpu_x86_properties;
}
static const TypeInfo x86_cpu_type_info = {
--
1.7.11.7
- [Qemu-devel] [PATCH 00/37 v5] target-i386: convert CPU features into properties, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 04/37] target-i386: filter out not TCG features if running without kvm at realize time, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 07/37] target-i386: use visit_type_hz to parse tsc_freq property value, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 02/37] target-i386: cpu_x86_register(): report error from property setter, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 10/37] target-i386: parse cpu_model string into set of stringified properties, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 01/37] target-i386: return Error from cpu_x86_find_by_name(), Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 03/37] target-i386: if x86_cpu_realize() failed report error and do cleanup, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 13/37] target-i386: convert "level" to static property, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 06/37] add visitor for parsing hz[KMG] input string, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 14/37] target-i386: postpone cpuid_level update to realize time, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 08/37] target-i386: define static properties for cpuid features,
Igor Mammedov <=
- [Qemu-devel] [PATCH 21/37] target-i386: convert 'hv_relaxed' to static property, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 11/37] target-i386: introduce vendor-override static property, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 28/37] target-i386: convert "model-id" to static property, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 20/37] target-i386: convert 'hv_spinlocks' to static property, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 19/37] qdev: add DEFINE_ABSTRACT_PROP() helper, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 34/37] qdev: introduce QDEV_FIND_PROP_FROM_BIT and qdev_prop_find_bit(), Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 25/37] target-i386: replace uint32_t vendor fields by vendor string in x86_def_t, Igor Mammedov, 2012/10/22
- [Qemu-devel] [PATCH 23/37] target-i386: convert 'check' and 'enforce' to static properties, Igor Mammedov, 2012/10/22