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[Qemu-devel] [Bug 1071149] Re: target-mips: special3 instruction dinsm t
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [Bug 1071149] Re: target-mips: special3 instruction dinsm translation error |
Date: |
Thu, 25 Oct 2012 07:57:03 -0000 |
That's why in gen_bitops() does later:
case OPC_DINSM:
if (lsb > msb)
goto fail;
mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) -
1) : ~0ULL) << lsb;
...
case OPC_DINSU:
if (lsb > msb)
goto fail;
mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32);
...
case OPC_DINS:
if (lsb > msb)
goto fail;
gen_load_gpr(t0, rt);
mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb;
For me there is no bug there, but if you believe the contrary, please
send a testcase.
** Changed in: qemu
Status: New => Invalid
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https://bugs.launchpad.net/bugs/1071149
Title:
target-mips: special3 instruction dinsm translation error
Status in QEMU:
Invalid
Bug description:
Function decode_opc() in translate.c calls function gen_bitops(),
which has such prototype:
/* special3 bitfield operations */
static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
int rs, int lsb, int msb)
The code for DINSM instruction is:
case OPC_DINSM ... OPC_DINS:
check_insn(env, ctx, ISA_MIPS64R2);
check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd);
break;
But rd ≠ msb according to MIPS64R2 standard, rd = msb - 32.
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