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[Qemu-devel] [PATCH v2 11/19] target-mips: optimize load operations
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v2 11/19] target-mips: optimize load operations |
Date: |
Tue, 30 Oct 2012 01:12:04 +0100 |
Only allocate t1 when needed.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-mips/translate.c | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 4485a81..c46129d 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1136,7 +1136,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx,
uint32_t opc,
}
t0 = tcg_temp_new();
- t1 = tcg_temp_new();
gen_base_offset_addr(ctx, t0, base, offset);
switch (opc) {
@@ -1159,29 +1158,35 @@ static void gen_ld (CPUMIPSState *env, DisasContext
*ctx, uint32_t opc,
break;
case OPC_LDL:
save_cpu_state(ctx, 1);
+ t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
+ tcg_temp_free(t1);
opn = "ldl";
break;
case OPC_LDR:
save_cpu_state(ctx, 1);
+ t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
+ tcg_temp_free(t1);
opn = "ldr";
break;
case OPC_LDPC:
- tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
+ t1 = tcg_const_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
+ tcg_temp_free(t1);
tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "ldpc";
break;
#endif
case OPC_LWPC:
- tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
+ t1 = tcg_const_tl(pc_relative_pc(ctx));
gen_op_addr_add(ctx, t0, t0, t1);
+ tcg_temp_free(t1);
tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
gen_store_gpr(t0, rt);
opn = "lwpc";
@@ -1213,16 +1218,20 @@ static void gen_ld (CPUMIPSState *env, DisasContext
*ctx, uint32_t opc,
break;
case OPC_LWL:
save_cpu_state(ctx, 1);
+ t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
+ tcg_temp_free(t1);
opn = "lwl";
break;
case OPC_LWR:
save_cpu_state(ctx, 1);
+ t1 = tcg_temp_new();
gen_load_gpr(t1, rt);
gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx);
gen_store_gpr(t1, rt);
+ tcg_temp_free(t1);
opn = "lwr";
break;
case OPC_LL:
@@ -1235,7 +1244,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx,
uint32_t opc,
(void)opn; /* avoid a compiler warning */
MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
tcg_temp_free(t0);
- tcg_temp_free(t1);
}
/* Store */
--
1.7.10.4
- [Qemu-devel] [PATCH v2 00/19] target-mips: misc fixes and optimizations, Aurelien Jarno, 2012/10/29
- [Qemu-devel] [PATCH v2 01/19] target-mips: correctly restore btarget upon exception, Aurelien Jarno, 2012/10/29
- [Qemu-devel] [PATCH v2 11/19] target-mips: optimize load operations,
Aurelien Jarno <=
- [Qemu-devel] [PATCH v2 02/19] target-mips: do not save CPU state when using retranslation, Aurelien Jarno, 2012/10/29
- [Qemu-devel] [PATCH v2 19/19] target-mips: don't flush extra TLB on permissions upgrade, Aurelien Jarno, 2012/10/29
- [Qemu-devel] [PATCH v2 07/19] target-mips: cleanup float to int conversion helpers, Aurelien Jarno, 2012/10/29
- [Qemu-devel] [PATCH v2 03/19] softfloat: implement fused multiply-add NaN propagation for MIPS, Aurelien Jarno, 2012/10/29
- [Qemu-devel] [PATCH v2 14/19] target-mips: don't use local temps for store conditional, Aurelien Jarno, 2012/10/29
- [Qemu-devel] [PATCH v2 13/19] target-mips: implement unaligned loads using TCG, Aurelien Jarno, 2012/10/29
- [Qemu-devel] [PATCH v2 15/19] target-mips: implement movn/movz using movcond, Aurelien Jarno, 2012/10/29
- [Qemu-devel] [PATCH v2 06/19] target-mips: fix FPU exceptions, Aurelien Jarno, 2012/10/29