Re: [Qemu-devel] Interrupt controller updates

[Peter Maydell]

On 22 November 2012 21:00, Benjamin Herrenschmidt
<address@hidden> wrote:
> Oh it's simple enough initially, just move the ioctl call from generic
> kvm init to machine init. The problem is then to add an argument, since
> that essentially means changing the ioctl number, but we need that for
> all archs where the interrupt subsystem can be fundamentally different
> based on the platform.

I cynically suspect there may need to be some disentangling of x86/qemu
code assumptions about what happens when, in order to do this "just
move" step :-)

> Basically, what was discussed in the BOF was that we split the init:
>
>  * The existing ioctl moves to early machine init (before VCPUs) and
> gets that argument to define the type of interrupt subsystem to use. It
> causes powerpc to instanciate ICPs per VCPUs for example. On archs that
> don't have a per-vcpu structure (equivalent of local APIC or ICP), all
> it does is enable subsequent irq related ioctls to work (it's just an
> "enable" flag).
>
>  * A new ioctl is used to actually instanciate external interrupt
> controllers (GIC on ARM, ICS for ppc/pseries, MPIC for ppc/mpic, ...).
> This is used later by the PIC code itself when the former ioctl has
> enabled "in kernel PIC"

For ARM we could move to use this but it would just be for the
benefit of nicer fallback behaviour (you could say "no in kernel
GIC" if the user runs qemu with a guest CPU which doesn't have a
GIC, rather than having to exit saying "incompatible options"
if 'in-kernel irqchip' and 'cpu with no irqchip' were both
specified).

>  * A new ioctl is used for platforms that need to be able to adjust the
> base address of a PIC (arm/GIC, ppc/mpic)

We have the ABI for this already in the kvm/arm patches which are
heading into final review, by the way.

-- PMM