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[Qemu-devel] [PATCH 2/6] hw/arm_gic: Fix comparison with priority mask r
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 2/6] hw/arm_gic: Fix comparison with priority mask register |
Date: |
Tue, 11 Dec 2012 15:22:36 +0000 |
The GIC spec states that only interrupts with higher priority
than the value in the GICC_PMR priority mask register are
passed through to the processor. We were incorrectly allowing
through interrupts with a priority equal to the specified
value: correct the comparison operation to match the spec.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Igor Mitsyanko <address@hidden>
---
hw/arm_gic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index f9e423f..672d539 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -73,7 +73,7 @@ void gic_update(GICState *s)
}
}
level = 0;
- if (best_prio <= s->priority_mask[cpu]) {
+ if (best_prio < s->priority_mask[cpu]) {
s->current_pending[cpu] = best_irq;
if (best_prio < s->running_priority[cpu]) {
DPRINTF("Raised pending IRQ %d\n", best_irq);
--
1.7.9.5
- [Qemu-devel] [PULL 0/6] arm-devs queue, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 1/6] hw/arm_boot, exynos4210, highbank: Fix secondary boot GIC init, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 6/6] exynos4210/mct: Avoid infinite loop on non incremental timers, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 4/6] xilinx_zynq: Add one variable to avoid overwriting QSPI bus, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 5/6] hw/arm_gic: fix target CPUs affected by set enable/pending ops, Peter Maydell, 2012/12/11
- [Qemu-devel] [PATCH 2/6] hw/arm_gic: Fix comparison with priority mask register,
Peter Maydell <=
- [Qemu-devel] [PATCH 3/6] hw/arm_gic_common: Correct GICC_PMR reset value for newer GICs, Peter Maydell, 2012/12/11