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Re: [Qemu-devel] [PATCH 03/15] openpic: fix sense and priority bits


From: Scott Wood
Subject: Re: [Qemu-devel] [PATCH 03/15] openpic: fix sense and priority bits
Date: Thu, 3 Jan 2013 14:12:35 -0600

On 01/03/2013 11:51:56 AM, Alexander Graf wrote:

On 22.12.2012, at 03:15, Scott Wood wrote:

> Previously, the sense and priority bits were masked off when writing
> to IVPR, and all interrupts were treated as edge-triggered (despite
> the existence of code for handling level-triggered interrupts).
>
> Polarity is implemented only as storage.  We don't simulate the
> bad effects that you'd get on real hardware if you set this incorrectly, > but at least the guest sees the right thing when it reads back the register.
>
> Sense now controls level/edge on FSL external interrupts (and all
> interrupts on non-FSL MPIC). FSL internal interrupts do not have a sense
> bit (reads as zero), but are level.  FSL timers and IPIs do not have
> sense or polarity bits (read as zero), and are edge-triggered.  To
> accommodate FSL internal interrupts, QEMU's internal notion of whether an
> interrupt is level-triggered is separated from the IVPR bit.
>
> Signed-off-by: Scott Wood <address@hidden>
> ---
> hw/openpic.c | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++------
> 1 file changed, 55 insertions(+), 6 deletions(-)
>
> diff --git a/hw/openpic.c b/hw/openpic.c
> index 02f793b..34449a7 100644
> --- a/hw/openpic.c
> +++ b/hw/openpic.c
> @@ -189,6 +189,9 @@ typedef struct IRQ_src_t {
>     uint32_t ide;   /* IRQ destination register */
>     int last_cpu;
>     int pending;    /* TRUE if IRQ is pending */
> +    bool level;     /* level-triggered */
> +    bool fslint;    /* FSL internal interrupt -- level only */
> + bool fslspecial; /* FSL timer/IPI interrupt, edge, no polarity */

This really looks more like an "irqtype" enum, no?

enum irqtype {
    IRQ_TYPE_NORMAL = 0,
    IRQ_TYPE_FSLINT,
    IRQ_TYPE_FSLSPECIAL,
}

OK. At one point they could both be set, before I looked more closely at how the special interrupts are defined in hardware.

-Scott



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