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Re: [Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN
From: |
Andreas Färber |
Subject: |
Re: [Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN |
Date: |
Thu, 24 Jan 2013 17:51:45 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130105 Thunderbird/17.0.2 |
Am 24.01.2013 05:03, schrieb Richard Henderson:
> As this is the first of the BMI insns to be implemented,
> this carries quite a bit more baggage than normal.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target-i386/cpu.c | 10 +++++-----
> target-i386/translate.c | 19 +++++++++++++++++--
> 2 files changed, 22 insertions(+), 7 deletions(-)
>
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 776b670..30893b6 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -399,12 +399,12 @@ typedef struct x86_def_t {
> #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
> CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
> #define TCG_SVM_FEATURES 0
> -#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
> +#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
> + CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2)
> /* missing:
> - CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_BMI1, CPUID_7_0_EBX_HLE,
> - CPUID_7_0_EBX_AVX2, CPUID_7_0_EBX_BMI2, CPUID_7_0_EBX_ERMS,
> - CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM, CPUID_7_0_EBX_RDSEED,
> - CPUID_7_0_EBX_ADX */
> + CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
> + CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
> + CPUID_7_0_EBX_RDSEED, CPUID_7_0_EBX_ADX */
>
> /* maintains list of cpu model definitions
> */
Note this will conflict with the upcoming 1.4 qom-cpu pull, which drops
the duplicate list built from the array.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
- [Qemu-devel] [PATCH 57/57] target-i386: Implement tzcnt and fix lzcnt, (continued)
- [Qemu-devel] [PATCH 57/57] target-i386: Implement tzcnt and fix lzcnt, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 33/57] target-i386: introduce gen_cmovcc1, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 31/57] target-i386: inline gen_prepare_cc_slow, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 40/57] target-i386: Use CC_SRC2 for ADC and SBB, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 35/57] target-i386: kill cpu_T3, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 49/57] target-i386: Implement BZHI, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 39/57] target-i386: optimize flags checking after sub using CC_SRC2, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 36/57] target-i386: use gen_op for cmps/scas, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 48/57] target-i386: Implement BLSR, BLSMSK, BLSI, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN, Richard Henderson, 2013/01/23
- Re: [Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN,
Andreas Färber <=
- [Qemu-devel] [PATCH 51/57] target-i386: Implement PDEP, PEXT, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 38/57] target-i386: Update cc_op before TCG branches, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 50/57] target-i386: Implement MULX, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 45/57] target-i386: Implement MOVBE, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 32/57] target-i386: cleanup temporary macros for CCPrepare, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 34/57] target-i386: expand cmov via movcond, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 37/57] target-i386: introduce gen_jcc1_noeob, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 52/57] target-i386: Implement SHLX, SARX, SHRX, Richard Henderson, 2013/01/23
- [Qemu-devel] [PATCH 20/57] target-i386: Move CC discards to set_cc_op, Richard Henderson, 2013/01/23