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[Qemu-devel] [PATCH 04/47] target-i386: Update X86CPU to QOM realizefn
From: |
Andreas Färber |
Subject: |
[Qemu-devel] [PATCH 04/47] target-i386: Update X86CPU to QOM realizefn |
Date: |
Sat, 16 Feb 2013 16:44:59 +0100 |
Adapt the signature of x86_cpu_realize(), hook up to
DeviceClass::realize and set realized = true in cpu_x86_init().
The QOM realizefn cannot depend on errp being non-NULL as in
cpu_x86_init(), so use a local Error to preserve error handling behavior
on APIC initialization errors.
Reviewed-by: Igor Mammedov <address@hidden>
Reviewed-by: Eduardo Habkost <address@hidden>
[AF: Invoke parent's realizefn]
Signed-off-by: Andreas Färber <address@hidden>
---
target-i386/cpu-qom.h | 5 ++---
target-i386/cpu.c | 19 +++++++++++++++----
target-i386/helper.c | 2 +-
3 Dateien geändert, 18 Zeilen hinzugefügt(+), 8 Zeilen entfernt(-)
diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index 332916a..48e6b54 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -39,6 +39,7 @@
/**
* X86CPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An x86 CPU model or family.
@@ -48,6 +49,7 @@ typedef struct X86CPUClass {
CPUClass parent_class;
/*< public >*/
+ DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} X86CPUClass;
@@ -72,8 +74,5 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
-/* TODO Drop once ObjectClass::realize is available */
-void x86_cpu_realize(Object *obj, Error **errp);
-
#endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index aab35c7..e2fd626 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2060,10 +2060,14 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
}
#endif
-void x86_cpu_realize(Object *obj, Error **errp)
+static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{
- X86CPU *cpu = X86_CPU(obj);
+ X86CPU *cpu = X86_CPU(dev);
+ X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
CPUX86State *env = &cpu->env;
+#ifndef CONFIG_USER_ONLY
+ Error *local_err = NULL;
+#endif
if (env->cpuid_7_0_ebx_features && env->cpuid_level < 7) {
env->cpuid_level = 7;
@@ -2105,8 +2109,9 @@ void x86_cpu_realize(Object *obj, Error **errp)
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) {
- x86_cpu_apic_init(cpu, errp);
- if (error_is_set(errp)) {
+ x86_cpu_apic_init(cpu, &local_err);
+ if (local_err != NULL) {
+ error_propagate(errp, local_err);
return;
}
}
@@ -2115,6 +2120,8 @@ void x86_cpu_realize(Object *obj, Error **errp)
mce_init(cpu);
qemu_init_vcpu(&cpu->env);
cpu_reset(CPU(cpu));
+
+ xcc->parent_realize(dev, errp);
}
/* Enables contiguous-apic-ID mode, for compatibility */
@@ -2200,6 +2207,10 @@ static void x86_cpu_common_class_init(ObjectClass *oc,
void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ xcc->parent_realize = dc->realize;
+ dc->realize = x86_cpu_realizefn;
xcc->parent_reset = cc->reset;
cc->reset = x86_cpu_reset;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index d1cb4e2..1a872fa 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1282,7 +1282,7 @@ X86CPU *cpu_x86_init(const char *cpu_model)
return NULL;
}
- x86_cpu_realize(OBJECT(cpu), &error);
+ object_property_set_bool(OBJECT(cpu), true, "realized", &error);
if (error) {
error_free(error);
object_unref(OBJECT(cpu));
--
1.7.10.4
- [Qemu-devel] [PULL 00/47] QOM CPUState patch queue 2013-02-16, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 02/47] target-alpha: Update AlphaCPU to QOM realizefn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 01/47] cpu: Prepare QOM realizefn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 03/47] target-arm: Update ARMCPU to QOM realizefn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 04/47] target-i386: Update X86CPU to QOM realizefn,
Andreas Färber <=
- [Qemu-devel] [PATCH 05/47] target-openrisc: Update OpenRISCCPU to QOM realizefn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 10/47] target-microblaze: Introduce QOM realizefn for MicroBlazeCPU, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 08/47] target-lm32: Introduce QOM realizefn for LM32CPU, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 06/47] target-ppc: Update PowerPCCPU to QOM realizefn, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 07/47] target-cris: Introduce QOM realizefn for CRISCPU, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 09/47] target-m68k: Introduce QOM realizefn for M68kCPU, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 12/47] target-s390x: Introduce QOM realizefn for S390CPU, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 15/47] target-unicore32: Introduce QOM realizefn for UniCore32CPU, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 11/47] target-mips: Introduce QOM realizefn for MIPSCPU, Andreas Färber, 2013/02/16
- [Qemu-devel] [PATCH 13/47] target-sh4: Introduce QOM realizefn for SuperHCPU, Andreas Färber, 2013/02/16