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[Qemu-devel] [PATCH 51/57] target-i386: Implement PDEP, PEXT
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 51/57] target-i386: Implement PDEP, PEXT |
Date: |
Tue, 19 Feb 2013 09:40:25 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target-i386/helper.h | 3 +++
target-i386/int_helper.c | 32 ++++++++++++++++++++++++++++++++
target-i386/translate.c | 36 ++++++++++++++++++++++++++++++++++++
3 files changed, 71 insertions(+)
diff --git a/target-i386/helper.h b/target-i386/helper.h
index d750754..81e0fbd 100644
--- a/target-i386/helper.h
+++ b/target-i386/helper.h
@@ -194,9 +194,12 @@ DEF_HELPER_3(fsave, void, env, tl, int)
DEF_HELPER_3(frstor, void, env, tl, int)
DEF_HELPER_3(fxsave, void, env, tl, int)
DEF_HELPER_3(fxrstor, void, env, tl, int)
+
DEF_HELPER_1(bsf, tl, tl)
DEF_HELPER_1(bsr, tl, tl)
DEF_HELPER_2(lzcnt, tl, tl, int)
+DEF_HELPER_FLAGS_2(pdep, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(pext, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* MMX/SSE */
diff --git a/target-i386/int_helper.c b/target-i386/int_helper.c
index 4ec8cb7..527af40 100644
--- a/target-i386/int_helper.c
+++ b/target-i386/int_helper.c
@@ -488,6 +488,38 @@ target_ulong helper_bsr(target_ulong t0)
return helper_lzcnt(t0, 0);
}
+#if TARGET_LONG_BITS == 32
+# define ctztl ctz32
+#else
+# define ctztl ctz64
+#endif
+
+target_ulong helper_pdep(target_ulong src, target_ulong mask)
+{
+ target_ulong dest = 0;
+ int i, o;
+
+ for (i = 0; mask != 0; i++) {
+ o = ctztl(mask);
+ mask &= mask - 1;
+ dest |= ((src >> i) & 1) << o;
+ }
+ return dest;
+}
+
+target_ulong helper_pext(target_ulong src, target_ulong mask)
+{
+ target_ulong dest = 0;
+ int i, o;
+
+ for (o = 0; mask != 0; o++) {
+ i = ctztl(mask);
+ mask &= mask - 1;
+ dest |= ((src >> i) & 1) << o;
+ }
+ return dest;
+}
+
#define SHIFT 0
#include "shift_helper_template.h"
#undef SHIFT
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 3017d63..51016fe 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4138,6 +4138,42 @@ static void gen_sse(CPUX86State *env, DisasContext *s,
int b,
}
break;
+ case 0x3f5: /* pdep Gy, By, Ey */
+ if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
+ || !(s->prefix & PREFIX_VEX)
+ || s->vex_l != 0) {
+ goto illegal_op;
+ }
+ ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
+ /* Note that by zero-extending the mask operand, we
+ automatically handle zero-extending the result. */
+ if (s->dflag == 2) {
+ tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
+ } else {
+ tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
+ }
+ gen_helper_pdep(cpu_regs[reg], cpu_T[0], cpu_T[1]);
+ break;
+
+ case 0x2f5: /* pext Gy, By, Ey */
+ if (!(s->cpuid_7_0_ebx_features & CPUID_7_0_EBX_BMI2)
+ || !(s->prefix & PREFIX_VEX)
+ || s->vex_l != 0) {
+ goto illegal_op;
+ }
+ ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
+ gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
+ /* Note that by zero-extending the mask operand, we
+ automatically handle zero-extending the result. */
+ if (s->dflag == 2) {
+ tcg_gen_mov_tl(cpu_T[1], cpu_regs[s->vex_v]);
+ } else {
+ tcg_gen_ext32u_tl(cpu_T[1], cpu_regs[s->vex_v]);
+ }
+ gen_helper_pext(cpu_regs[reg], cpu_T[0], cpu_T[1]);
+ break;
+
case 0x0f3:
case 0x1f3:
case 0x2f3:
--
1.8.1.2
- [Qemu-devel] [PATCH 27/57] target-i386: optimize setcc instructions, (continued)
- [Qemu-devel] [PATCH 27/57] target-i386: optimize setcc instructions, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 19/57] target-i386: no need to flush out cc_op before gen_eob, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 35/57] target-i386: kill cpu_T3, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 50/57] target-i386: Implement MULX, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 09/57] target-i386: compute eflags outside rcl/rcr helper, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 06/57] target-i386: drop cc_op argument of gen_jcc1, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 46/57] target-i386: Implement ANDN, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 54/57] target-i386: Implement ADX extension, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 20/57] target-i386: Move CC discards to set_cc_op, Richard Henderson, 2013/02/19
- Re: [Qemu-devel] [PATCH v3 00/57] target-i386 flags improvements and bmi/adx extensions, Paolo Bonzini, 2013/02/19
- [Qemu-devel] [PATCH 51/57] target-i386: Implement PDEP, PEXT,
Richard Henderson <=
- [Qemu-devel] [PATCH 12/57] target-i386: factor gen_op_set_cc_op/tcg_gen_discard_tl around computing flags, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 14/57] target-i386: Introduce set_cc_op, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 55/57] target-i386: Use clz/ctz for bsf/bsr helpers, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 10/57] target-i386: clean up sahf, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 13/57] target-i386: Name the cc_op enumeration, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 11/57] target-i386: use gen_jcc1 to compile loopz, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 34/57] target-i386: expand cmov via movcond, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 07/57] target-i386: move carry computation for inc/dec closer to gen_op_set_cc_op, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 57/57] target-i386: Add CC_OP_CLR, Richard Henderson, 2013/02/19
- [Qemu-devel] [PATCH 29/57] target-i386: introduce gen_prepare_cc, Richard Henderson, 2013/02/19