[Qemu-devel] [PATCH 21/48] mmu-hash*: Combine ppc_hash{32, 64}_get_physical_address and get_segment{32, 64}()

[David Gibson]

After previous work, ppc_hash{32,64}_get_physical_address() are almost
trivial wrappers around get_segment{32,64}() which does nearly all the work of
translating an address according to the hash mmu model.  Therefore combine the
two functions into one, under the better name of
ppc_hash{32,64}_translate().

Signed-off-by: David Gibson <address@hidden>
---
 target-ppc/mmu-hash32.c |   49 +++++++++++++++++++----------------------------
 target-ppc/mmu-hash64.c |   37 +++++++++++++++--------------------
 2 files changed, 35 insertions(+), 51 deletions(-)

diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index 8001563..bc97834 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -376,8 +376,8 @@ static int find_pte32(CPUPPCState *env, struct 
mmu_ctx_hash32 *ctx,
     return ret;
 }
 
-static int get_segment32(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
-                         target_ulong eaddr, int rwx)
+static int ppc_hash32_translate(CPUPPCState *env, struct mmu_ctx_hash32 *ctx,
+                                target_ulong eaddr, int rwx)
 {
     hwaddr hash;
     target_ulong vsid;
@@ -385,6 +385,22 @@ static int get_segment32(CPUPPCState *env, struct 
mmu_ctx_hash32 *ctx,
     int ret, ret2;
     target_ulong sr, pgidx;
 
+    /* 1. Handle real mode accesses */
+    if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
+        /* Translation is off */
+        ctx->raddr = eaddr;
+        ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
+        return 0;
+    }
+
+    /* 2. Check Block Address Translation entries (BATs) */
+    if (env->nb_BATs != 0) {
+        ret = ppc_hash32_get_bat(env, ctx, eaddr, rwx);
+        if (ret == 0) {
+            return 0;
+        }
+    }
+
     pr = msr_pr;
 
     sr = env->sr[eaddr >> 28];
@@ -521,38 +537,13 @@ static int get_segment32(CPUPPCState *env, struct 
mmu_ctx_hash32 *ctx,
     return ret;
 }
 
-static int ppc_hash32_get_physical_address(CPUPPCState *env, struct 
mmu_ctx_hash32 *ctx,
-                                           target_ulong eaddr, int rwx)
-{
-    bool real_mode = (rwx == 2 && msr_ir == 0)
-        || (rwx != 2 && msr_dr == 0);
-
-    if (real_mode) {
-        ctx->raddr = eaddr;
-        ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
-        return 0;
-    } else {
-        int ret = -1;
-
-        /* Try to find a BAT */
-        if (env->nb_BATs != 0) {
-            ret = ppc_hash32_get_bat(env, ctx, eaddr, rwx);
-        }
-        if (ret < 0) {
-            /* We didn't match any BAT entry or don't have BATs */
-            ret = get_segment32(env, ctx, eaddr, rwx);
-        }
-        return ret;
-    }
-}
-
 hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
 {
     struct mmu_ctx_hash32 ctx;
 
     /* FIXME: Will not behave sanely for direct store segments, but
      * they're almost never used */
-    if (unlikely(ppc_hash32_get_physical_address(env, &ctx, addr, 0)
+    if (unlikely(ppc_hash32_translate(env, &ctx, addr, 0)
                  != 0)) {
         return -1;
     }
@@ -566,7 +557,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, 
target_ulong address, int rwx,
     struct mmu_ctx_hash32 ctx;
     int ret = 0;
 
-    ret = ppc_hash32_get_physical_address(env, &ctx, address, rwx);
+    ret = ppc_hash32_translate(env, &ctx, address, rwx);
     if (ret == 0) {
         tlb_set_page(env, address & TARGET_PAGE_MASK,
                      ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 407c6e6..9afc418 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -434,19 +434,28 @@ static int find_pte64(CPUPPCState *env, struct 
mmu_ctx_hash64 *ctx,
     return ret;
 }
 
-static int get_segment64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
-                         target_ulong eaddr, int rwx)
+static int ppc_hash64_translate(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
+                                target_ulong eaddr, int rwx)
 {
     hwaddr hash;
     target_ulong vsid;
     int pr, target_page_bits;
     int ret, ret2;
-
-    pr = msr_pr;
     ppc_slb_t *slb;
     target_ulong pageaddr;
     int segment_bits;
 
+    /* 1. Handle real mode accesses */
+    if (((rwx == 2) && (msr_ir == 0)) || ((rwx != 2) && (msr_dr == 0))) {
+        /* Translation is off */
+        /* In real mode the top 4 effective address bits are ignored */
+        ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
+        ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
+        return 0;
+    }
+
+    pr = msr_pr;
+
     LOG_MMU("Check SLBs\n");
     slb = slb_lookup(env, eaddr);
     if (!slb) {
@@ -518,27 +527,11 @@ static int get_segment64(CPUPPCState *env, struct 
mmu_ctx_hash64 *ctx,
     return ret;
 }
 
-static int ppc_hash64_get_physical_address(CPUPPCState *env,
-                                           struct mmu_ctx_hash64 *ctx,
-                                           target_ulong eaddr, int rwx)
-{
-    bool real_mode = (rwx == 2 && msr_ir == 0)
-        || (rwx != 2 && msr_dr == 0);
-
-    if (real_mode) {
-        ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
-        ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
-        return 0;
-    } else {
-        return get_segment64(env, ctx, eaddr, rwx);
-    }
-}
-
 hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
 {
     struct mmu_ctx_hash64 ctx;
 
-    if (unlikely(ppc_hash64_get_physical_address(env, &ctx, addr, 0) != 0)) {
+    if (unlikely(ppc_hash64_translate(env, &ctx, addr, 0) != 0)) {
         return -1;
     }
 
@@ -551,7 +544,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, 
target_ulong address, int rwx,
     struct mmu_ctx_hash64 ctx;
     int ret = 0;
 
-    ret = ppc_hash64_get_physical_address(env, &ctx, address, rwx);
+    ret = ppc_hash64_translate(env, &ctx, address, rwx);
     if (ret == 0) {
         tlb_set_page(env, address & TARGET_PAGE_MASK,
                      ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
-- 
1.7.10.4