Re: [Qemu-devel] [PATCH v3 08/20] tcg-arm: Implement deposit for armv7

[Peter Maydell]

On 28 March 2013 15:32, Richard Henderson <address@hidden> wrote:
> We have BFI and BFC available for implementing it.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  tcg/arm/tcg-target.c | 36 ++++++++++++++++++++++++++++++++++++
>  tcg/arm/tcg-target.h |  5 ++++-
>  2 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
> index 88f5689..4950eaf 100644
> --- a/tcg/arm/tcg-target.c
> +++ b/tcg/arm/tcg-target.c
> @@ -702,6 +702,35 @@ static inline void tcg_out_bswap32(TCGContext *s, int 
> cond, int rd, int rn)
>      }
>  }
>
> +bool tcg_target_deposit_valid(int ofs, int len)
> +{
> +    /* ??? Without bfi, we could improve over generic code by combining
> +       the right-shift from a non-zero ofs with the orr.  We do run into
> +       problems when rd == rs, and the mask generated from ofs+len don't
> +       fit into an immediate.  We would have to be careful not to pessimize
> +       wrt the optimizations performed on the expanded code.  */
> +    return use_armv7_instructions;

Strictly speaking BFI is v6T2, but there doesn't seem much point
in making the distinction given it would only affect the rare
ARM1156. (Personally I don't think there's much point worrying about
optmising codegen for anything pre-v7 at all.)

> +}
> +
> +static inline void tcg_out_deposit(TCGContext *s, int cond, TCGReg rd,
> +                                   TCGArg a1, int ofs, int len, bool 
> const_a1)
> +{
> +    if (const_a1) {
> +        uint32_t mask = (2u << (len - 1)) - 1;

What guarantees us that we won't see a length of 0?
The tcg/README description doesn't say that's invalid
and I don't think the optimize pass handles it (maybe I
missed it).

-- PMM