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[Qemu-devel] [PATCH v5 27/33] tcg-ppc64: Use MFOCRF instead of MFCR
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v5 27/33] tcg-ppc64: Use MFOCRF instead of MFCR |
Date: |
Mon, 15 Apr 2013 20:41:06 +0200 |
It takes half the cycles to read one CR register instead of all 8.
This is a backward compatible addition to the ISA, so chips prior
to Power 2.00 spec will simply continue to read the entire CR register.
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc64/tcg-target.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index 70cbb86..c7800b0 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -382,6 +382,7 @@ static int tcg_target_const_match (tcg_target_long val,
#define SRAWI XO31(824)
#define NEG XO31(104)
#define MFCR XO31( 19)
+#define MFOCRF (MFCR | (1u << 20))
#define NOR XO31(124)
#define CNTLZW XO31( 26)
#define CNTLZD XO31( 58)
@@ -430,6 +431,7 @@ static int tcg_target_const_match (tcg_target_long val,
#define ME(e) ((e)<<1)
#define BO(o) ((o)<<21)
#define MB64(b) ((b)<<5)
+#define FXM(b) (1 << (19 - (b)))
#define LK 1
@@ -1226,10 +1228,12 @@ static void tcg_out_setcond (TCGContext *s, TCGType
type, TCGCond cond,
sh = 31;
crop = CRNOR | BT (7, CR_EQ) | BA (7, CR_GT) | BB (7, CR_GT);
crtest:
- tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, type);
- if (crop) tcg_out32 (s, crop);
- tcg_out32 (s, MFCR | RT (0));
- tcg_out_rlw(s, RLWINM, arg0, 0, sh, 31, 31);
+ tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
+ if (crop) {
+ tcg_out32(s, crop);
+ }
+ tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
+ tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
break;
default:
--
1.8.1.4
- [Qemu-devel] [PATCH v5 17/33] tcg-ppc64: Streamline qemu_ld/st insn selection, (continued)
- [Qemu-devel] [PATCH v5 17/33] tcg-ppc64: Streamline qemu_ld/st insn selection, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 18/33] tcg-ppc64: Implement rotates, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 19/33] tcg-ppc64: Implement bswap16 and bswap32, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 20/33] tcg-ppc64: Implement bswap64, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 22/33] tcg-ppc64: Handle constant inputs for some compound logicals, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 23/33] tcg-ppc64: Implement deposit, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 24/33] tcg-ppc64: Use I constraint for mul, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 25/33] tcg-ppc64: Use TCGType throughout compares, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 26/33] tcg-ppc64: Cleanup i32 constants to tcg_out_cmp, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 27/33] tcg-ppc64: Use MFOCRF instead of MFCR,
Richard Henderson <=
- [Qemu-devel] [PATCH v5 28/33] tcg-ppc64: Use ISEL for setcond, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 30/33] tcg-ppc64: Use getauxval for ISA detection, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 31/33] tcg-ppc64: Implement add2/sub2_i64, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 32/33] tcg-ppc64: Implement mulu2/muls2_i64, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 33/33] tcg-ppc64: Handle deposit of zero, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 29/33] tcg-ppc64: Implement movcond, Richard Henderson, 2013/04/15
- [Qemu-devel] [PATCH v5 21/33] tcg-ppc64: Implement compound logicals, Richard Henderson, 2013/04/15
- Re: [Qemu-devel] [PATCH v5 00/33] Modernize tcg/ppc64, Aurelien Jarno, 2013/04/15