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[Qemu-devel] [PATCH v2 05/10] target-ppc: emulate prtyw and prtyd instru
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [PATCH v2 05/10] target-ppc: emulate prtyw and prtyd instructions |
Date: |
Sat, 20 Apr 2013 20:56:17 +0200 |
Needed for Power ISA version 2.05 compliance.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
---
target-ppc/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 6bee6db..977f9ef 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1458,6 +1458,42 @@ static void gen_popcntd(DisasContext *ctx)
}
#endif
+/* prtyw: PowerPC 2.05 specification */
+static void gen_prtyw(DisasContext *ctx)
+{
+ TCGv ra = cpu_gpr[rA(ctx->opcode)];
+ TCGv rs = cpu_gpr[rS(ctx->opcode)];
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_shri_tl(t0, rs, 16);
+ tcg_gen_xor_tl(ra, rs, t0);
+ tcg_gen_shri_tl(t0, ra, 8);
+ tcg_gen_xor_tl(ra, ra, t0);
+#if defined(TARGET_PPC64)
+ tcg_gen_andi_tl(ra, ra, 0x100000001);
+#else
+ tcg_gen_andi_tl(ra, ra, 1);
+#endif
+ tcg_temp_free(t0);
+}
+
+#if defined(TARGET_PPC64)
+/* prtyd: PowerPC 2.05 specification */
+static void gen_prtyd(DisasContext *ctx)
+{
+ TCGv ra = cpu_gpr[rA(ctx->opcode)];
+ TCGv rs = cpu_gpr[rS(ctx->opcode)];
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_shri_tl(t0, rs, 32);
+ tcg_gen_xor_tl(ra, rs, t0);
+ tcg_gen_shri_tl(t0, ra, 16);
+ tcg_gen_xor_tl(ra, ra, t0);
+ tcg_gen_shri_tl(t0, ra, 8);
+ tcg_gen_xor_tl(ra, ra, t0);
+ tcg_gen_andi_tl(ra, ra, 1);
+ tcg_temp_free(t0);
+}
+#endif
+
#if defined(TARGET_PPC64)
/* extsw & extsw. */
GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
@@ -8489,9 +8525,11 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000,
PPC_INTEGER),
GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
+GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
#if defined(TARGET_PPC64)
GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
+GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
#endif
GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
--
1.7.10.4
[Qemu-devel] [PATCH v2 09/10] target-ppc: emulate store doubleword pair instructions, Aurelien Jarno, 2013/04/20
[Qemu-devel] [PATCH v2 03/10] target-ppc: add instruction flags for Book I 2.05, Aurelien Jarno, 2013/04/20
[Qemu-devel] [PATCH v2 07/10] target-ppc: emulate lfiwax instruction, Aurelien Jarno, 2013/04/20
[Qemu-devel] [PATCH v2 04/10] target-ppc: emulate cmpb instruction, Aurelien Jarno, 2013/04/20
[Qemu-devel] [PATCH v2 06/10] target-ppc: emulate fcpsgn instruction, Aurelien Jarno, 2013/04/20
[Qemu-devel] [PATCH v2 08/10] target-ppc: emulate load doubleword pair instructions, Aurelien Jarno, 2013/04/20