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Re: [Qemu-devel] [SeaBIOS] KVM call agenda for 2013-05-28

From: David Woodhouse
Subject: Re: [Qemu-devel] [SeaBIOS] KVM call agenda for 2013-05-28
Date: Fri, 31 May 2013 13:16:34 +0100

On Wed, 2013-05-29 at 21:12 -0400, Kevin O'Connor wrote:
> I remain doubtful that QOM has all the info needed to generate the
> BIOS tables.  Does QOM describe how the 5th pci device uses global
> interrupt 11 when using global interrupts, legacy interrupt 5 when not
> using global interrupts, and that the legacy interrupt can be changed
> by writing to the 0x60 address of the 1st pci device's config space?
> Does QOM state that the machine supports S3 sleep mode?  Does QOM
> indicate that an IPMI device supports the 3rd version of the IPMI
> device specification?

Does it indicate whether this particular version of qemu has correctly
implemented the hard reset at 0xcf9? If so, we need to put that in as

It seems that there's a *lot* which isn't fully described in the QOM
tree. Do we really want to add it all, just so that ACPI tables can be
reliably generated from it? 

As we add new types of hardware and even fix/adjust features like the
examples above, we'll also have to implement the translation from QOM to
ACPI tables. And we'll have to do so in more than one place, in projects
with a completely different release cycle. This would be *so* much
easier if the code which actually generates the ACPI tables was *in* the
qemu tree along with the "hardware" that those tables describe.


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