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[Qemu-devel] [PULL 03/24] xilinx_spips: Inhibit interrupts in LQSPI mode
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/24] xilinx_spips: Inhibit interrupts in LQSPI mode |
Date: |
Mon, 3 Jun 2013 17:30:00 +0100 |
From: Peter Crosthwaite <address@hidden>
The real hardware does not produce interrupts in LQSPI mode. Inhibit
generation of interrupts when the LQ_MODE bit is set.
Signed-off-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/ssi/xilinx_spips.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 261d948..a8691d5 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -204,6 +204,9 @@ static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
static void xilinx_spips_update_ixr(XilinxSPIPS *s)
{
+ if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
+ return;
+ }
/* These are set/cleared as they occur */
s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
IXR_TX_FIFO_MODE_FAIL);
@@ -256,7 +259,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
for (i = 0; i < num_effective_busses(s); ++i) {
if (!i || s->snoop_state == SNOOP_STRIPING) {
if (fifo8_is_empty(&s->tx_fifo)) {
- s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
+ if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
+ s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
+ }
xilinx_spips_update_ixr(s);
return;
} else {
--
1.7.9.5
- [Qemu-devel] [PULL 10/24] xilinx_spips: Fix CTRL register RW bits, (continued)
- [Qemu-devel] [PULL 10/24] xilinx_spips: Fix CTRL register RW bits, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 14/24] xilinx_spips: lqspi: Push more data to tx-fifo, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 24/24] i.MX: Improve EPIT timer code., Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 12/24] xilinx_spips: Debug msgs for Snoop state, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 13/24] xilinx_spips: Multiple debug verbosity levels, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 06/24] xilinx_spips: Trash LQ page cache on mode change, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 15/24] xilinx_spips: lqspi: Fix byte/misaligned access, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 19/24] sd/sdhci:ADMA: fix interrupt, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 23/24] exynos4210.c: register rom_mem for memory migration, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 16/24] sd/sdhci.c: Only reset data_count on new commands, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 03/24] xilinx_spips: Inhibit interrupts in LQSPI mode,
Peter Maydell <=
- [Qemu-devel] [PULL 05/24] xilinx_spips: Fix QSPI FIFO size, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 04/24] xilinx_spips: Add verbose LQSPI debug output, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 21/24] i.MX: split GPT and EPIT timer implementation, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 17/24] sd/sdhci: Fix Buffer Write Ready interrupt, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 08/24] xilinx_spips: Implement automatic CS, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 22/24] hw/arm/exynos4210.c: convert chipid_and_omr to an mmio region, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 02/24] xilinx_spips: Make interrupts clear on read, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 07/24] xilinx_spips: Add automatic start support, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 20/24] sd/sd.c: Fix "inquiry" ACMD41, Peter Maydell, 2013/06/03
- [Qemu-devel] [PULL 11/24] xilinx_spips: Fix striping behaviour, Peter Maydell, 2013/06/03