Re: [Qemu-devel] [PATCH v3 08/14] tcg-arm: Make use of conditional availability of opcodes for divide

[Peter Maydell]

On 3 July 2013 22:29, Richard Henderson <address@hidden> wrote:
> We can now detect and use divide instructions at runtime, rather than
> having to restrict their availability to compile-time.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
>  tcg/arm/tcg-target.c | 16 ++++++++++++++--
>  tcg/arm/tcg-target.h | 14 ++++++++------
>  2 files changed, 22 insertions(+), 8 deletions(-)
>
> diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
> index 8321f80..2c46ceb 100644
> --- a/tcg/arm/tcg-target.c
> +++ b/tcg/arm/tcg-target.c
> @@ -67,6 +67,13 @@ static const int use_armv7_instructions = 0;
>  #endif
>  #undef USE_ARMV7_INSTRUCTIONS
>
> +#ifndef use_idiv_instructions
> +bool use_idiv_instructions;
> +#endif
> +#ifdef CONFIG_GETAUXVAL
> +# include <sys/auxv.h>
> +#endif

My ARM system doesn't have a sys/auxv.h, which renders most of this patch
a bit moot (and certainly untestable :-)). Do newer glibc have this?

> +
>  #ifndef NDEBUG
>  static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
>      "%r0",
> @@ -2029,16 +2036,21 @@ static const TCGTargetOpDef arm_op_defs[] = {
>
>      { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
>
> -#if TCG_TARGET_HAS_div_i32
>      { INDEX_op_div_i32, { "r", "r", "r" } },
>      { INDEX_op_divu_i32, { "r", "r", "r" } },
> -#endif
>
>      { -1 },
>  };
>
>  static void tcg_target_init(TCGContext *s)
>  {
> +#if defined(CONFIG_GETAUXVAL) && !defined(use_idiv_instructions)
> +    {
> +        unsigned long hwcap = getauxval(AT_HWCAP);
> +        use_idiv_instructions = hwcap & (HWCAP_ARM_IDIVA | HWCAP_ARM_IDIVT);

Doesn't this mean we'll try to use the ARM division
insns even if the CPU only supports the Thumb encodings?
I think you should only be testing for whether HWCAP_ARM_IDIVA
is set.

> +    }
> +#endif

thanks
-- PMM