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[Qemu-devel] [PATCH v2 4/7] AARCH64: Add boot support for aarch64 proces
From: |
Mian M. Hamayun |
Subject: |
[Qemu-devel] [PATCH v2 4/7] AARCH64: Add boot support for aarch64 processor |
Date: |
Tue, 23 Jul 2013 11:33:13 +0200 |
From: "Mian M. Hamayun" <address@hidden>
This version supports booting of a single Aarch64 CPU by setting appropriate
registers. The bootloader includes placehoders for Board-ID that are used to
implementing uniform indexing across different bootloaders. The same macro
names are used with different values when compiling for different processors.
Signed-off-by: Mian M. Hamayun <address@hidden>
Conflicts:
hw/arm/boot.c
---
hw/arm/boot.c | 44 +++++++++++++++++++++++++++++++++++++++-----
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 7cca2b3..b9b0beb 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -18,7 +18,33 @@
#include "qemu/config-file.h"
#define KERNEL_ARGS_ADDR 0x100
-#define KERNEL_LOAD_ADDR 0x00010000
+
+#ifdef TARGET_AARCH64
+#define KERNEL_LOAD_ADDR 0x00080000
+#define KERNEL_ARGS_INDEX 6
+#define KERNEL_ENTRY_INDEX 8
+#define KERNEL_BOARDID_INDEX 10
+
+static uint32_t bootloader[] = {
+ 0x580000c0, /* ldr x0, 18 ; Load the lower 32-bits of DTB */
+ 0xaa1f03e1, /* mov x1, xzr */
+ 0xaa1f03e2, /* mov x2, xzr */
+ 0xaa1f03e3, /* mov x3, xzr */
+ 0x58000084, /* ldr x4, 20 ; Load the lower 32-bits of kernel entry
*/
+ 0xd61f0080, /* br x4 ; Jump to the kernel entry point */
+ 0x00000000, /* .word @DTB Lower 32-bits */
+ 0x00000000, /* .word @DTB Higher 32-bits */
+ 0x00000000, /* .word @Kernel Entry Lower 32-bits */
+ 0x00000000, /* .word @Kernel Entry Higher 32-bits */
+ 0x00000000, /* .word @Board ID Lower 32-bits -- Placeholder */
+ 0x00000000 /* .word @Board ID Higher 32-bits -- Placeholder */
+};
+
+#else
+#define KERNEL_LOAD_ADDR 0x00010000
+#define KERNEL_BOARDID_INDEX 4
+#define KERNEL_ARGS_INDEX 5
+#define KERNEL_ENTRY_INDEX 6
/* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */
static uint32_t bootloader[] = {
@@ -30,6 +56,7 @@ static uint32_t bootloader[] = {
0, /* Address of kernel args. Set by integratorcp_init. */
0 /* Kernel entry point. Set by integratorcp_init. */
};
+#endif
/* Handling for secondary CPU boot in a multicore system.
* Unlike the uniprocessor/primary CPU boot, this is platform
@@ -341,8 +368,15 @@ static void do_cpu_reset(void *opaque)
env->regs[15] = info->entry & 0xfffffffe;
env->thumb = info->entry & 1;
} else {
+#ifdef TARGET_AARCH64
+ env->pstate = PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT |
PSR_MODE_EL1h;
+#endif
if (env == first_cpu) {
+#ifdef TARGET_AARCH64
+ env->pc = info->loader_start;
+#else
env->regs[15] = info->loader_start;
+#endif
if (!info->dtb_filename) {
if (old_param) {
set_kernel_args_old(info);
@@ -447,7 +481,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info
*info)
}
info->initrd_size = initrd_size;
- bootloader[4] = info->board_id;
+ bootloader[KERNEL_BOARDID_INDEX] = info->board_id;
/* for device tree boot, we pass the DTB directly in r2. Otherwise
* we point to the kernel args.
@@ -462,9 +496,9 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info
*info)
if (load_dtb(dtb_start, info)) {
exit(1);
}
- bootloader[5] = dtb_start;
+ bootloader[KERNEL_ARGS_INDEX] = dtb_start;
} else {
- bootloader[5] = info->loader_start + KERNEL_ARGS_ADDR;
+ bootloader[KERNEL_ARGS_INDEX] = info->loader_start +
KERNEL_ARGS_ADDR;
if (info->ram_size >= (1ULL << 32)) {
fprintf(stderr, "qemu: RAM size must be less than 4GB to boot"
" Linux kernel using ATAGS (try passing a device tree"
@@ -472,7 +506,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info
*info)
exit(1);
}
}
- bootloader[6] = entry;
+ bootloader[KERNEL_ENTRY_INDEX] = entry;
for (n = 0; n < sizeof(bootloader) / 4; n++) {
bootloader[n] = tswap32(bootloader[n]);
}
--
1.7.9.5
- [Qemu-devel] [PATCH v2 0/7] AARCH64 support on machvirt machine model using KVM, Mian M. Hamayun, 2013/07/23
- [Qemu-devel] [PATCH v2 4/7] AARCH64: Add boot support for aarch64 processor,
Mian M. Hamayun <=
- [Qemu-devel] [PATCH v2 5/7] AARCH64: Disable the non-aarch64 specific reset code, Mian M. Hamayun, 2013/07/23
- [Qemu-devel] [PATCH v2 3/7] AARCH64: Add aarch64 CPU initialization, get and put registers support, Mian M. Hamayun, 2013/07/23
- [Qemu-devel] [PATCH v2 6/7] AARCH64: Add SMP support for aarch64 processors, Mian M. Hamayun, 2013/07/23
- [Qemu-devel] [PATCH v2 7/7] AARCH64: Use the spin-table method for booting secondary processors in machvirt, Mian M. Hamayun, 2013/07/23